[PATCH] D67021: [DAGCombiner] improve throughput of shift+logic+shift

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri marked an inline comment as done.
lebedev.ri added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7217-7219
+  if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR &&
+      LogicOpcode != ISD::XOR)
+    return SDValue();
----------------
spatel wrote:
> lebedev.ri wrote:
> > Is there some function already that has whitelist of such bitwise ops?
> > I suspect there are more candidates.
> Target-specific opcodes? And/or/xor are the only generic opcodes that I am aware of.
Right yes, i was talking about target-specific ones.


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  https://reviews.llvm.org/D67021/new/

https://reviews.llvm.org/D67021