[PATCH] D67046: [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

We need a proper scheduling model for this patch to be tested.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67046

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D67046.218242.patch
Type: text/x-patch
Size: 5011 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190831/31288610/attachment.bin>