[PATCH] D66973: [RISCV] Switch to the Machine Scheduler

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, jfb, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, qcolombet.
Herald added a project: LLVM.

Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact.

One concern is that some reorderings break relaxable instruction pairs, such as `lui`/`addi` with `%*hi` and `%*lo` relocations. (Grepping with `grep -C1 "%.*hi" *.ll` in `llvm/test/CodeGen/RISCV` shows that in most tests such instructions are still in sequential pairs). We might need a proper machine model to fix that, but that would be a separate patch.

A few tests that had to be manually updated are worth additional review attention:

  rv64i-complex-float.ll
  compress.ll
  callee-saved-fpr32s.ll
  callee-saved-fpr64s.ll
  callee-saved-gprs.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66973

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/add-before-shl.ll
  llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
  llvm/test/CodeGen/RISCV/addcarry.ll
  llvm/test/CodeGen/RISCV/alloca.ll
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/arith-with-overflow.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/bare-select.ll
  llvm/test/CodeGen/RISCV/blockaddress.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-fcmp.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-select-fcmp.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-fcmp.ll
  llvm/test/CodeGen/RISCV/float-imm.ll
  llvm/test/CodeGen/RISCV/float-intrinsics.ll
  llvm/test/CodeGen/RISCV/float-mem.ll
  llvm/test/CodeGen/RISCV/float-select-fcmp.ll
  llvm/test/CodeGen/RISCV/fp128.ll
  llvm/test/CodeGen/RISCV/frame-info.ll
  llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
  llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
  llvm/test/CodeGen/RISCV/imm-cse.ll
  llvm/test/CodeGen/RISCV/imm.ll
  llvm/test/CodeGen/RISCV/indirectbr.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm.ll
  llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
  llvm/test/CodeGen/RISCV/legalize-fneg.ll
  llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
  llvm/test/CodeGen/RISCV/mem.ll
  llvm/test/CodeGen/RISCV/mem64.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/remat.ll
  llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
  llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
  llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/setcc-logic.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/split-offsets.ll
  llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll