[PATCH] D66752: [RISCV] Implement RISCVRegisterInfo::getPointerRegClass

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
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`TargetRegisterInfo::getPointerRegClass` is used, directly and indirectly, by several passes and CodeGen so it should be implemented (overridden) for RISC-V too.

@reshabh This will probably affect your GSoC work implementing 64-bit pointers on RV32. Not sure what the status of that is and how you want to proceed, but I imagine you'll just tweak this method once this patch is committed?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66752

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -52,6 +52,12 @@
   bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
     return true;
   }
+
+  const TargetRegisterClass *
+  getPointerRegClass(const MachineFunction &MF,
+                     unsigned Kind = 0) const override {
+    return &RISCV::GPRRegClass;
+  }
 };
 }
 


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