[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri requested changes to this revision.
lebedev.ri added a comment.
This revision now requires changes to proceed.

(Just marking as reviewed) Based on previous disscussion let me know if i should try to take this over.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66571/new/

https://reviews.llvm.org/D66571