[PATCH] D67021: [DAGCombiner] improve throughput of shift+logic+shift

Sat Aug 31 02:30:14 PDT 2019

lebedev.ri added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/bitfield-insert.ll:269
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    lsl w8, w8, #8
+; CHECK-NEXT:    mov w9, w8
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efriedma wrote:
> Not really related to your patch, but I'm surprised we aren't matching the and+lsl to ubfiz.  Something odd going on with the zext, I guess: we lower the zext to a mask, but then don't switch the "and" with the shift like instcombine would.  (Simplified example: "int a(unsigned char x) { return x*8; }", vs. "int a(int x) { return ((unsigned char)x)*8; }".)
> 
> If that gets fixed, it looks like this saves one instruction, maybe?  Not sure what effect that fix would have on the old code.
Random mention that i'm seeing similar issue in https://reviews.llvm.org/D62100#change-c0aDpsCUsZ0a
That patch is stuck due to that i think :/

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67021/new/

https://reviews.llvm.org/D67021