[llvm] r370528 - [AArch64] add tests for shift-logic-shift; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Aug 30 13:48:43 2019
New Revision: 370528

URL: http://llvm.org/viewvc/llvm-project?rev=370528&view=rev
Log:
[AArch64] add tests for shift-logic-shift; NFC

Added:
    llvm/trunk/test/CodeGen/AArch64/shift-logic.ll

Added: llvm/trunk/test/CodeGen/AArch64/shift-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/shift-logic.ll?rev=370528&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/shift-logic.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/shift-logic.ll Fri Aug 30 13:48:43 2019
@@ -0,0 +1,150 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+
+define i32 @shl_and(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: shl_and:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w1, w0, lsl #5
+; CHECK-NEXT:    lsl w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = shl i32 %x, 5
+  %r = and i32 %sh0, %y
+  %sh1 = shl i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @shl_or(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: shl_or:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr w8, w1, w0, lsl #5
+; CHECK-NEXT:    lsl w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = shl i32 %x, 5
+  %r = or i32 %y, %sh0
+  %sh1 = shl i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @shl_xor(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: shl_xor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w1, w0, lsl #5
+; CHECK-NEXT:    lsl w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = shl i32 %x, 5
+  %r = xor i32 %sh0, %y
+  %sh1 = shl i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @lshr_and(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: lshr_and:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w1, w0, lsr #5
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = lshr i32 %x, 5
+  %r = and i32 %y, %sh0
+  %sh1 = lshr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @lshr_or(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: lshr_or:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr w8, w1, w0, lsr #5
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = lshr i32 %x, 5
+  %r = or i32 %sh0, %y
+  %sh1 = lshr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @lshr_xor(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: lshr_xor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w1, w0, lsr #5
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = lshr i32 %x, 5
+  %r = xor i32 %y, %sh0
+  %sh1 = lshr i32 %r, 7
+  ret i32 %sh1
+}
+
+
+define i32 @ashr_and(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: ashr_and:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w1, w0, asr #5
+; CHECK-NEXT:    asr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = ashr i32 %x, 5
+  %r = and i32 %y, %sh0
+  %sh1 = ashr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @ashr_or(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: ashr_or:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr w8, w1, w0, asr #5
+; CHECK-NEXT:    asr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = ashr i32 %x, 5
+  %r = or i32 %sh0, %y
+  %sh1 = ashr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @ashr_xor(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: ashr_xor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w1, w0, asr #5
+; CHECK-NEXT:    asr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = ashr i32 %x, 5
+  %r = xor i32 %y, %sh0
+  %sh1 = ashr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @shr_mismatch_xor(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: shr_mismatch_xor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w1, w0, asr #5
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    ret
+  %sh0 = ashr i32 %x, 5
+  %r = xor i32 %y, %sh0
+  %sh1 = lshr i32 %r, 7
+  ret i32 %sh1
+}
+
+define i32 @ashr_overshift_xor(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: ashr_overshift_xor:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w1, w0, asr #15
+; CHECK-NEXT:    asr w0, w8, #17
+; CHECK-NEXT:    ret
+  %sh0 = ashr i32 %x, 15
+  %r = xor i32 %y, %sh0
+  %sh1 = ashr i32 %r, 17
+  ret i32 %sh1
+}
+
+define i32 @lshr_or_extra_use(i32 %x, i32 %y, i32* %p) nounwind {
+; CHECK-LABEL: lshr_or_extra_use:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr w8, w1, w0, lsr #5
+; CHECK-NEXT:    lsr w0, w8, #7
+; CHECK-NEXT:    str w8, [x2]
+; CHECK-NEXT:    ret
+  %sh0 = lshr i32 %x, 5
+  %r = or i32 %sh0, %y
+  store i32 %r, i32* %p
+  %sh1 = lshr i32 %r, 7
+  ret i32 %sh1
+}
+