[llvm] r370393 - [X86] Remove what little support we had for MPX
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 11:47:47 PDT 2019
Why? I can get deprecating the intrinsics or even removing them, but
why pretend the processors don't support it?
Philip
On 8/29/19 11:09 AM, Craig Topper via llvm-commits wrote:
> Author: ctopper
> Date: Thu Aug 29 11:09:02 2019
> New Revision: 370393
>
> URL: http://llvm.org/viewvc/llvm-project?rev=370393&view=rev
> Log:
> [X86] Remove what little support we had for MPX
>
> -Deprecate -mmpx and -mno-mpx command line options
> -Remove CPUID detection of mpx for -march=native
> -Remove MPX from all CPUs
> -Remove MPX preprocessor define
>
> I've left the "mpx" string in the backend so we don't fail on old IR, but its not connected to anything.
>
> gcc has also deprecated these command line options. https://www.phoronix.com/scan.php?page=news_item&px=GCC-Patch-To-Drop-MPX
>
> Differential Revision: https://reviews.llvm.org/D66669
>
> Modified:
> llvm/trunk/docs/ReleaseNotes.rst
> llvm/trunk/lib/Support/Host.cpp
> llvm/trunk/lib/Target/X86/X86.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrMPX.td
> llvm/trunk/lib/Target/X86/X86Subtarget.h
> llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll
> llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll
>
> Modified: llvm/trunk/docs/ReleaseNotes.rst
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.rst?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/docs/ReleaseNotes.rst (original)
> +++ llvm/trunk/docs/ReleaseNotes.rst Thu Aug 29 11:09:02 2019
> @@ -98,6 +98,10 @@ Changes to the AVR Target
>
> During this release ...
>
> +* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
> + intrinsics for this feature. This change only this effects the results
> + returned by getHostCPUFeatures on CPUs that implement the MPX instructions.
> +
> Changes to the WebAssembly Target
> ---------------------------------
>
>
> Modified: llvm/trunk/lib/Support/Host.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Support/Host.cpp (original)
> +++ llvm/trunk/lib/Support/Host.cpp Thu Aug 29 11:09:02 2019
> @@ -1378,7 +1378,6 @@ bool sys::getHostCPUFeatures(StringMap<b
> Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
> Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
> Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
> - Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1);
> // AVX512 is only supported if the OS supports the context save for it.
> Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
> Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
>
> Modified: llvm/trunk/lib/Target/X86/X86.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86.td (original)
> +++ llvm/trunk/lib/Target/X86/X86.td Thu Aug 29 11:09:02 2019
> @@ -241,8 +241,11 @@ def FeatureCLDEMOTE : SubtargetFeature<
> "Enable Cache Demote">;
> def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
> "Support ptwrite instruction">;
> -def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
> - "Support MPX instructions">;
> +// FIXME: This feature is deprecated in 10.0 and should not be used for
> +// anything, but removing it would break IR files that may contain it in a
> +// target-feature attribute.
> +def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false",
> + "Deprecated. Support MPX instructions">;
> def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
> "Use LEA for adjusting the stack pointer">;
> def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
> @@ -580,7 +583,6 @@ def ProcessorFeatures {
>
> // Skylake
> list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
> - FeatureMPX,
> FeatureXSAVEC,
> FeatureXSAVES,
> FeatureCLFLUSHOPT,
> @@ -719,7 +721,6 @@ def ProcessorFeatures {
>
> // Goldmont
> list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
> - FeatureMPX,
> FeatureSHA,
> FeatureRDSEED,
> FeatureXSAVE,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Aug 29 11:09:02 2019
> @@ -940,7 +940,6 @@ def HasMOVDIR64B : Predicate<"Subtarget-
> def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">;
> def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
> def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
> -def HasMPX : Predicate<"Subtarget->hasMPX()">;
> def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">;
> def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
> def HasCLWB : Predicate<"Subtarget->hasCLWB()">;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrMPX.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMPX.td?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrMPX.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrMPX.td Thu Aug 29 11:09:02 2019
> @@ -12,16 +12,16 @@
> //
> //===----------------------------------------------------------------------===//
>
> -// FIXME: Investigate a better scheduler class once MPX is used inside LLVM.
> +// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM.
> let SchedRW = [WriteSystem] in {
>
> multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
> def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
> OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
> - Requires<[HasMPX, Not64BitMode]>;
> + Requires<[Not64BitMode]>;
> def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
> OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
> - Requires<[HasMPX, In64BitMode]>;
> + Requires<[In64BitMode]>;
> }
>
> defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
> @@ -29,17 +29,17 @@ defm BNDMK : mpx_bound_make<0x1B, "bndmk
> multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
> def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
> OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
> - Requires<[HasMPX, Not64BitMode]>;
> + Requires<[Not64BitMode]>;
> def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
> OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
> - Requires<[HasMPX, In64BitMode]>;
> + Requires<[In64BitMode]>;
>
> def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
> OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
> - Requires<[HasMPX, Not64BitMode]>;
> + Requires<[Not64BitMode]>;
> def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
> OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
> - Requires<[HasMPX, In64BitMode]>;
> + Requires<[In64BitMode]>;
> }
> defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
> defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
> @@ -47,33 +47,31 @@ defm BNDCN : mpx_bound_check<0x1B, "bndc
>
> def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX]>, NotMemoryFoldable;
> + NotMemoryFoldable;
> let mayLoad = 1 in {
> def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
> + Requires<[Not64BitMode]>, NotMemoryFoldable;
> def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
> + Requires<[In64BitMode]>, NotMemoryFoldable;
> }
> let isCodeGenOnly = 1, ForceDisassemble = 1 in
> def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX]>, NotMemoryFoldable;
> + NotMemoryFoldable;
> let mayStore = 1 in {
> def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
> + Requires<[Not64BitMode]>, NotMemoryFoldable;
> def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
> "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
> - Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
> + Requires<[In64BitMode]>, NotMemoryFoldable;
>
> def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
> - "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
> - Requires<[HasMPX]>;
> + "bndstx\t{$src, $dst|$dst, $src}", []>, PS;
> }
> let mayLoad = 1 in
> def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
> - "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
> - Requires<[HasMPX]>;
> + "bndldx\t{$src, $dst|$dst, $src}", []>, PS;
> } // SchedRW
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Aug 29 11:09:02 2019
> @@ -365,8 +365,8 @@ protected:
> /// Processor has AVX-512 vp2intersect instructions
> bool HasVP2INTERSECT = false;
>
> - /// Processor supports MPX - Memory Protection Extensions
> - bool HasMPX = false;
> + /// Deprecated flag for MPX instructions.
> + bool DeprecatedHasMPX = false;
>
> /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
> /// using Shadow Stack
> @@ -684,7 +684,6 @@ public:
> bool hasBF16() const { return HasBF16; }
> bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
> bool hasBITALG() const { return HasBITALG; }
> - bool hasMPX() const { return HasMPX; }
> bool hasSHSTK() const { return HasSHSTK; }
> bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
> bool hasCLWB() const { return HasCLWB; }
>
> Modified: llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/ms-inline-asm-avx512.ll Thu Aug 29 11:09:02 2019
> @@ -20,5 +20,5 @@ entry:
> ; CHECK: movq %rax, 7(%rsp)
> ; CHECK: retq
>
> -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { nounwind }
>
> Modified: llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll?rev=370393&r1=370392&r2=370393&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-width-store-merge.ll Thu Aug 29 11:09:02 2019
> @@ -46,8 +46,8 @@ entry:
> ; Function Attrs: argmemonly nounwind
> declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1 immarg) #1
>
> -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
> attributes #1 = { argmemonly nounwind }
> -attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
> +attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
>
> !0 = !{i32 1, !"wchar_size", i32 4}
>
>
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