[llvm] r370382 - [GlobalISel][AArch64] Select llvm.aarch64.stxr* intrinsics.
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 09:55:55 PDT 2019
Author: paquette
Date: Thu Aug 29 09:55:55 2019
New Revision: 370382
URL: http://llvm.org/viewvc/llvm-project?rev=370382&view=rev
Log:
[GlobalISel][AArch64] Select llvm.aarch64.stxr* intrinsics.
Add a GISelPredicateCode to the stxr_* PatFrags in AArch64InstrAtomics.td.
This allows us to select these intrinsics.
Differential Revision: https://reviews.llvm.org/D65779
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td
llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td?rev=370382&r1=370381&r2=370382&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td Thu Aug 29 09:55:55 2019
@@ -287,22 +287,30 @@ def : Pat<(and (ldaxr_4 GPR64sp:$addr),
def stxr_1 : PatFrag<(ops node:$val, node:$ptr),
(int_aarch64_stxr node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 1); }];
+}
def stxr_2 : PatFrag<(ops node:$val, node:$ptr),
(int_aarch64_stxr node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 2); }];
+}
def stxr_4 : PatFrag<(ops node:$val, node:$ptr),
(int_aarch64_stxr node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 4); }];
+}
def stxr_8 : PatFrag<(ops node:$val, node:$ptr),
(int_aarch64_stxr node:$val, node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 8); }];
+}
def : Pat<(stxr_1 GPR64:$val, GPR64sp:$addr),
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir?rev=370382&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-stx.mir Thu Aug 29 09:55:55 2019
@@ -0,0 +1,122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ define void @test_store_i8(i32, i8 %val, i8* %addr) { ret void }
+ define void @test_store_i16(i32, i16 %val, i16* %addr) { ret void }
+ define void @test_store_i32(i32, i32 %val, i32* %addr) { ret void }
+ define void @test_store_i64(i32, i64 %val, i64* %addr) { ret void }
+...
+---
+name: test_store_i8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w0, $w1, $x2
+
+ ; CHECK-LABEL: name: test_store_i8
+ ; CHECK: liveins: $w0, $w1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
+ ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
+ ; CHECK: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store 1 into %ir.addr)
+ ; CHECK: $w0 = COPY %5
+ ; CHECK: RET_ReallyLR implicit $w0
+ %3:gpr(s32) = COPY $w1
+ %2:gpr(p0) = COPY $x2
+ %6:gpr(s64) = G_CONSTANT i64 255
+ %7:gpr(s64) = G_ANYEXT %3(s32)
+ %4:gpr(s64) = G_AND %7, %6
+ %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store 1 into %ir.addr)
+ $w0 = COPY %5(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: test_store_i16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w0, $w1, $x2
+
+ ; CHECK-LABEL: name: test_store_i16
+ ; CHECK: liveins: $w0, $w1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
+ ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
+ ; CHECK: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store 2 into %ir.addr)
+ ; CHECK: $w0 = COPY %5
+ ; CHECK: RET_ReallyLR implicit $w0
+ %3:gpr(s32) = COPY $w1
+ %2:gpr(p0) = COPY $x2
+ %6:gpr(s64) = G_CONSTANT i64 65535
+ %7:gpr(s64) = G_ANYEXT %3(s32)
+ %4:gpr(s64) = G_AND %7, %6
+ %5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %4(s64), %2(p0) :: (volatile store 2 into %ir.addr)
+ $w0 = COPY %5(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: test_store_i32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w0, $w1, $x2
+
+ ; CHECK-LABEL: name: test_store_i32
+ ; CHECK: liveins: $w0, $w1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
+ ; CHECK: early-clobber %3:gpr32 = STXRW [[COPY]], [[COPY1]] :: (volatile store 4 into %ir.addr)
+ ; CHECK: $w0 = COPY %3
+ ; CHECK: RET_ReallyLR implicit $w0
+ %1:gpr(s32) = COPY $w1
+ %2:gpr(p0) = COPY $x2
+ %3:gpr(s64) = G_ZEXT %1(s32)
+ %4:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %3(s64), %2(p0) :: (volatile store 4 into %ir.addr)
+ $w0 = COPY %4(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: test_store_i64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w0, $x1, $x2
+
+ ; CHECK-LABEL: name: test_store_i64
+ ; CHECK: liveins: $w0, $x1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
+ ; CHECK: early-clobber %2:gpr32 = STXRX [[COPY]], [[COPY1]] :: (volatile store 8 into %ir.addr)
+ ; CHECK: $w0 = COPY %2
+ ; CHECK: RET_ReallyLR implicit $w0
+ %1:gpr(s64) = COPY $x1
+ %2:gpr(p0) = COPY $x2
+ %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stxr), %1(s64), %2(p0) :: (volatile store 8 into %ir.addr)
+ $w0 = COPY %3(s32)
+ RET_ReallyLR implicit $w0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll?rev=370382&r1=370381&r2=370382&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll Thu Aug 29 09:55:55 2019
@@ -113,39 +113,57 @@ declare i64 @llvm.aarch64.ldxr.p0i16(i16
declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
+; FALLBACK-NOT: remark:{{.*}}test_store_i8
define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb
; CHECK-NOT: and
; CHECK: stxrb w0, w1, [x2]
+; GISEL-LABEL: test_store_i8:
+; GISEL-NOT: uxtb
+; GISEL-NOT: and
+; GISEL: stxrb w0, w1, [x2]
%extval = zext i8 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
ret i32 %res
}
+; FALLBACK-NOT: remark:{{.*}}test_store_i16
define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth
; CHECK-NOT: and
; CHECK: stxrh w0, w1, [x2]
+; GISEL-LABEL: test_store_i16:
+; GISEL-NOT: uxth
+; GISEL-NOT: and
+; GISEL: stxrh w0, w1, [x2]
%extval = zext i16 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
ret i32 %res
}
+; FALLBACK-NOT: remark:{{.*}}test_store_i32
define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
; CHECK-LABEL: test_store_i32:
; CHECK-NOT: uxtw
; CHECK-NOT: and
; CHECK: stxr w0, w1, [x2]
+; GISEL-LABEL: test_store_i32:
+; GISEL-NOT: uxtw
+; GISEL-NOT: and
+; GISEL: stxr w0, w1, [x2]
%extval = zext i32 %val to i64
%res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
ret i32 %res
}
+; FALLBACK-NOT: remark:{{.*}}test_store_i64
define i32 @test_store_i64(i32, i64 %val, i64* %addr) {
; CHECK-LABEL: test_store_i64:
; CHECK: stxr w0, x1, [x2]
+; GISEL-LABEL: test_store_i64:
+; GISEL: stxr w0, x1, [x2]
%res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
ret i32 %res
}
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