[llvm] r370280 - GlobalISel/TableGen: Handle setcc patterns
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 28 18:13:41 PDT 2019
Author: arsenm
Date: Wed Aug 28 18:13:41 2019
New Revision: 370280
URL: http://llvm.org/viewvc/llvm-project?rev=370280&view=rev
Log:
GlobalISel/TableGen: Handle setcc patterns
This is a special case because one node maps to two different G_
instructions, and the operand order is changed.
This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
llvm/trunk/test/TableGen/GlobalISelEmitter-setcc.td
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.td
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
llvm/trunk/test/TableGen/Common/GlobalISelEmitterCommon.td
llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelector.h Wed Aug 28 18:13:41 2019
@@ -208,6 +208,12 @@ enum {
/// - Expected Intrinsic ID
GIM_CheckIntrinsicID,
+ /// Check the operand is a specific predicate
+ /// - InsnID - Instruction ID
+ /// - OpIdx - Operand index
+ /// - Expected predicate
+ GIM_CheckCmpPredicate,
+
/// Check the specified operand is an MBB
/// - InsnID - Instruction ID
/// - OpIdx - Operand index
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h Wed Aug 28 18:13:41 2019
@@ -662,7 +662,21 @@ bool InstructionSelector::executeMatchTa
return false;
break;
}
-
+ case GIM_CheckCmpPredicate: {
+ int64_t InsnID = MatchTable[CurrentIdx++];
+ int64_t OpIdx = MatchTable[CurrentIdx++];
+ int64_t Value = MatchTable[CurrentIdx++];
+ DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+ dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
+ << InsnID << "]->getOperand(" << OpIdx
+ << "), Value=" << Value << ")\n");
+ assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
+ MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
+ if (!MO.isPredicate() || MO.getPredicate() != Value)
+ if (handleReject() == RejectAndGiveUp)
+ return false;
+ break;
+ }
case GIM_CheckIsMBB: {
int64_t InsnID = MatchTable[CurrentIdx++];
int64_t OpIdx = MatchTable[CurrentIdx++];
Modified: llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (original)
+++ llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td Wed Aug 28 18:13:41 2019
@@ -34,6 +34,10 @@ class GINodeEquiv<Instruction i, SDNode
// depending on the predicates on the node.
Instruction IfSignExtend = ?;
Instruction IfZeroExtend = ?;
+
+ // SelectionDAG has one setcc for all compares. This differentiates
+ // for G_ICMP and G_FCMP.
+ Instruction IfFloatingPoint = ?;
}
// These are defined in the same order as the G_* instructions.
@@ -122,6 +126,11 @@ def : GINodeEquiv<G_LOAD, ld> {
let IfSignExtend = G_SEXTLOAD;
let IfZeroExtend = G_ZEXTLOAD;
}
+
+def : GINodeEquiv<G_ICMP, setcc> {
+ let IfFloatingPoint = G_FCMP;
+}
+
// Broadly speaking G_STORE is equivalent to ISD::STORE but there are some
// complications that tablegen must take care of. For example, predicates such
// as isTruncStore require that this is not a perfect 1:1 mapping since a
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Wed Aug 28 18:13:41 2019
@@ -643,16 +643,32 @@ def assertzext : SDNode<"ISD::AssertZext
//===----------------------------------------------------------------------===//
// Selection DAG Condition Codes
-class CondCode; // ISD::CondCode enums
-def SETOEQ : CondCode; def SETOGT : CondCode;
-def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
-def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
-def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
-def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
-
-def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
-def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
+class CondCode<string fcmpName = "", string icmpName = ""> {
+ string ICmpPredicate = icmpName;
+ string FCmpPredicate = fcmpName;
+}
+// ISD::CondCode enums, and mapping to CmpInst::Predicate names
+def SETOEQ : CondCode<"FCMP_OEQ">;
+def SETOGT : CondCode<"FCMP_OGT">;
+def SETOGE : CondCode<"FCMP_OGE">;
+def SETOLT : CondCode<"FCMP_OLT">;
+def SETOLE : CondCode<"FCMP_OLE">;
+def SETONE : CondCode<"FCMP_ONE">;
+def SETO : CondCode<"FCMP_ORD">;
+def SETUO : CondCode<"FCMP_UNO">;
+def SETUEQ : CondCode<"FCMP_UEQ">;
+def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">;
+def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">;
+def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
+def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">;
+def SETUNE : CondCode<"FCMP_UNE">;
+def SETEQ : CondCode<"", "ICMP_EQ">;
+def SETGT : CondCode<"", "ICMP_SGT">;
+def SETGE : CondCode<"", "ICMP_SGE">;
+def SETLT : CondCode<"", "ICMP_SLT">;
+def SETLE : CondCode<"", "ICMP_SLE">;
+def SETNE : CondCode<"", "ICMP_NE">;
//===----------------------------------------------------------------------===//
// Selection DAG Node Transformation Functions.
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Wed Aug 28 18:13:41 2019
@@ -163,11 +163,10 @@ unsigned AMDGPURegisterBankInfo::getBrea
const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
const TargetRegisterClass &RC) const {
+ if (&RC == &AMDGPU::SReg_1RegClass)
+ return AMDGPU::VCCRegBank;
- if (TRI->isSGPRClass(&RC))
- return getRegBank(AMDGPU::SGPRRegBankID);
-
- return getRegBank(AMDGPU::VGPRRegBankID);
+ return TRI->isSGPRClass(&RC) ? AMDGPU::SGPRRegBank : AMDGPU::VGPRRegBank;
}
template <unsigned NumOps>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.td?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBanks.td Wed Aug 28 18:13:41 2019
@@ -17,4 +17,4 @@ def VGPRRegBank : RegisterBank<"VGPR",
def SCCRegBank : RegisterBank <"SCC", [SReg_32, SCC_CLASS]>;
// It is helpful to distinguish conditions from ordinary SGPRs.
-def VCCRegBank : RegisterBank <"VCC", [SReg_64]>;
+def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir?rev=370280&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir Wed Aug 28 18:13:41 2019
@@ -0,0 +1,799 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE32 %s
+
+---
+name: fcmp_false_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_false_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_false_s32_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(false), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_oeq_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_oeq_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oeq_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ogt_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ogt_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ogt_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_oge_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_oge_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oge_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_olt_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_olt_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_olt_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ole_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ole_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ole_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_one_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_one_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_one_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ord_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ord_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ord_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_uno_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_uno_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uno_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ueq_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ueq_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ueq_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ugt_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ugt_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ugt_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_uge_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_uge_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uge_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ult_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ult_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ult_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ule_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ule_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ule_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_une_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_une_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
+ ; WAVE32-LABEL: name: fcmp_une_s32_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_true_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_true_s32_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_true_s32_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vcc(s1) = G_FCMP floatpred(true), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_false_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_false_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_false_s64_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(false), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_oeq_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_oeq_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oeq_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ogt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ogt_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ogt_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_oge_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_oge_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oge_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_olt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_olt_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_olt_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ole_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ole_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ole_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_one_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_one_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_one_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ord_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ord_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ord_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_uno_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_uno_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uno_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ueq_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ueq_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ueq_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ugt_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ugt_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ugt_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_uge_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_uge_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uge_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ult_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ult_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ult_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_ule_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_ule_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ule_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_une_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_une_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
+ ; WAVE32-LABEL: name: fcmp_une_s64_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fcmp_true_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; WAVE64-LABEL: name: fcmp_true_s64_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_true_s64_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vcc(s1) = G_FCMP floatpred(true), %0, %1
+ S_ENDPGM 0, implicit %2
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir?rev=370280&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir Wed Aug 28 18:13:41 2019
@@ -0,0 +1,441 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE32 %s
+
+---
+name: fcmp_false_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_false_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_false_s16_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(false), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_oeq_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_oeq_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oeq_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ogt_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ogt_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ogt_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_oge_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_oge_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_oge_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_olt_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_olt_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_olt_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ole_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ole_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ole_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+---
+name: fcmp_one_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_one_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_one_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ord_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ord_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ord_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_uno_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_uno_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uno_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ueq_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ueq_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ueq_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ugt_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ugt_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ugt_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_uge_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_uge_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_uge_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ult_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ult_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ult_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_ule_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_ule_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_ule_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_une_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_une_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
+ ; WAVE32-LABEL: name: fcmp_une_s16_vv
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
+ ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(une), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
+---
+name: fcmp_true_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; WAVE64-LABEL: name: fcmp_true_s16_vv
+ ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
+ ; WAVE32-LABEL: name: fcmp_true_s16_vv
+ ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+ ; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vcc(s1) = G_FCMP floatpred(true), %2, %3
+ S_ENDPGM 0, implicit %4
+...
+
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir Wed Aug 28 18:13:41 2019
@@ -49,11 +49,9 @@ body: |
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
- ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
- ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 1
- ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
+ ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]]
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
; MIPS32: RetRA
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll Wed Aug 28 18:13:41 2019
@@ -290,8 +290,7 @@ define i64 @shl_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
-; MIPS32-NEXT: xor $9, $6, $8
-; MIPS32-NEXT: sltiu $9, $9, 1
+; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: sllv $10, $4, $6
; MIPS32-NEXT: srlv $3, $4, $3
; MIPS32-NEXT: sllv $6, $5, $6
@@ -321,10 +320,8 @@ define i64 @ashl_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
-; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
-; MIPS32-NEXT: xor $8, $6, $8
-; MIPS32-NEXT: sltiu $8, $8, 1
+; MIPS32-NEXT: sltiu $8, $6, 1
; MIPS32-NEXT: srav $9, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
@@ -354,8 +351,7 @@ define i64 @lshr_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
-; MIPS32-NEXT: xor $9, $6, $8
-; MIPS32-NEXT: sltiu $9, $9, 1
+; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: srlv $10, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll Wed Aug 28 18:13:41 2019
@@ -164,8 +164,6 @@ define i1 @eq_i64(i64 %a, i64 %b){
; MIPS32-NEXT: xor $1, $4, $6
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: or $1, $1, $2
-; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: xor $1, $1, $2
; MIPS32-NEXT: sltiu $2, $1, 1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -180,8 +178,6 @@ define i1 @ne_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: xor $1, $4, $6
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: or $1, $1, $2
-; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: xor $1, $1, $2
; MIPS32-NEXT: sltu $2, $zero, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll Wed Aug 28 18:13:41 2019
@@ -186,8 +186,6 @@ define void @umul_with_overflow(i32 %lhs
; MIPS32-NEXT: mul $1, $4, $5
; MIPS32-NEXT: multu $4, $5
; MIPS32-NEXT: mfhi $2
-; MIPS32-NEXT: ori $3, $zero, 0
-; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: sltu $2, $zero, $2
; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: and $2, $2, $3
Modified: llvm/trunk/test/TableGen/Common/GlobalISelEmitterCommon.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/Common/GlobalISelEmitterCommon.td?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/test/TableGen/Common/GlobalISelEmitterCommon.td (original)
+++ llvm/trunk/test/TableGen/Common/GlobalISelEmitterCommon.td Wed Aug 28 18:13:41 2019
@@ -7,6 +7,7 @@ def GPR32 : RegisterClass<"MyTarget", [i
def GPR32Op : RegisterOperand<GPR32>;
def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
+def FPR32Op : RegisterOperand<FPR32>;
def p0 : PtrValueType <i32, 0>;
class I<dag OOps, dag IOps, list<dag> Pat>
Added: llvm/trunk/test/TableGen/GlobalISelEmitter-setcc.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter-setcc.td?rev=370280&view=auto
==============================================================================
--- llvm/trunk/test/TableGen/GlobalISelEmitter-setcc.td (added)
+++ llvm/trunk/test/TableGen/GlobalISelEmitter-setcc.td Wed Aug 28 18:13:41 2019
@@ -0,0 +1,24 @@
+// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
+// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+// GISEL: GIM_Try
+// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
+// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP,
+// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
+def FCMPOEQ : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
+ [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>;
+
+// GISEL: GIM_Try
+// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
+// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ICMP,
+// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+def ICMPEQ : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32:$src1),
+ [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>;
+
+// Check there is an error if not a CondCode operand.
+// ERR: [[FILE]]:[[@LINE+1]]:1: warning: Skipped pattern: Unable to handle CondCode
+def FCMP_NOTCC : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
+ [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, i32)))]>;
Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=370280&r1=370279&r2=370280&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Wed Aug 28 18:13:41 2019
@@ -1064,6 +1064,7 @@ public:
OPM_SameOperand,
OPM_ComplexPattern,
OPM_IntrinsicID,
+ OPM_CmpPredicate,
OPM_Instruction,
OPM_Int,
OPM_LiteralInt,
@@ -1389,6 +1390,36 @@ public:
}
};
+/// Generates code to check that an operand is an CmpInst predicate
+class CmpPredicateOperandMatcher : public OperandPredicateMatcher {
+protected:
+ std::string PredName;
+
+public:
+ CmpPredicateOperandMatcher(unsigned InsnVarID, unsigned OpIdx,
+ std::string P)
+ : OperandPredicateMatcher(OPM_CmpPredicate, InsnVarID, OpIdx), PredName(P) {}
+
+ bool isIdentical(const PredicateMatcher &B) const override {
+ return OperandPredicateMatcher::isIdentical(B) &&
+ PredName == cast<CmpPredicateOperandMatcher>(&B)->PredName;
+ }
+
+ static bool classof(const PredicateMatcher *P) {
+ return P->getKind() == OPM_CmpPredicate;
+ }
+
+ void emitPredicateOpcodes(MatchTable &Table,
+ RuleMatcher &Rule) const override {
+ Table << MatchTable::Opcode("GIM_CheckCmpPredicate")
+ << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
+ << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
+ << MatchTable::Comment("Predicate")
+ << MatchTable::NamedValue("CmpInst", PredName)
+ << MatchTable::LineBreak;
+ }
+};
+
/// Generates code to check that an operand is an intrinsic ID.
class IntrinsicIDOperandMatcher : public OperandPredicateMatcher {
protected:
@@ -3256,6 +3287,13 @@ Record *GlobalISelEmitter::findNodeEquiv
const CodeGenInstruction *
GlobalISelEmitter::getEquivNode(Record &Equiv, const TreePatternNode *N) const {
+ if (N->getNumChildren() >= 1) {
+ // setcc operation maps to two different G_* instructions based on the type.
+ if (!Equiv.isValueUnset("IfFloatingPoint") &&
+ MVT(N->getChild(0)->getSimpleType(0)).isFloatingPoint())
+ return &Target.getInstruction(Equiv.getValueAsDef("IfFloatingPoint"));
+ }
+
for (const TreePredicateCall &Call : N->getPredicateCalls()) {
const TreePredicateFn &Predicate = Call.Fn;
if (!Equiv.isValueUnset("IfSignExtend") && Predicate.isLoad() &&
@@ -3265,6 +3303,7 @@ GlobalISelEmitter::getEquivNode(Record &
Predicate.isZeroExtLoad())
return &Target.getInstruction(Equiv.getValueAsDef("IfZeroExtend"));
}
+
return &Target.getInstruction(Equiv.getValueAsDef("I"));
}
@@ -3505,6 +3544,34 @@ Expected<InstructionMatcher &> GlobalISe
return InsnMatcher;
}
+ // Special case because the operand order is changed from setcc. The
+ // predicate operand needs to be swapped from the last operand to the first
+ // source.
+
+ unsigned NumChildren = Src->getNumChildren();
+ bool IsFCmp = SrcGIOrNull->TheDef->getName() == "G_FCMP";
+
+ if (IsFCmp || SrcGIOrNull->TheDef->getName() == "G_ICMP") {
+ TreePatternNode *SrcChild = Src->getChild(NumChildren - 1);
+ if (SrcChild->isLeaf()) {
+ DefInit *DI = dyn_cast<DefInit>(SrcChild->getLeafValue());
+ Record *CCDef = DI ? DI->getDef() : nullptr;
+ if (!CCDef || !CCDef->isSubClassOf("CondCode"))
+ return failedImport("Unable to handle CondCode");
+
+ OperandMatcher &OM =
+ InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx);
+ StringRef PredType = IsFCmp ? CCDef->getValueAsString("FCmpPredicate") :
+ CCDef->getValueAsString("ICmpPredicate");
+
+ if (!PredType.empty()) {
+ OM.addPredicate<CmpPredicateOperandMatcher>(PredType);
+ // Process the other 2 operands normally.
+ --NumChildren;
+ }
+ }
+ }
+
// Match the used operands (i.e. the children of the operator).
bool IsIntrinsic =
SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
@@ -3513,7 +3580,7 @@ Expected<InstructionMatcher &> GlobalISe
if (IsIntrinsic && !II)
return failedImport("Expected IntInit containing intrinsic ID)");
- for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {
+ for (unsigned i = 0; i != NumChildren; ++i) {
TreePatternNode *SrcChild = Src->getChild(i);
// SelectionDAG allows pointers to be represented with iN since it doesn't
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