[llvm] r370204 - [SelectionDAG] Don't generate libcalls for wide shifts on Windows (PR42711)
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 28 06:55:11 PDT 2019
Author: hans
Date: Wed Aug 28 06:55:10 2019
New Revision: 370204
URL: http://llvm.org/viewvc/llvm-project?rev=370204&view=rev
Log:
[SelectionDAG] Don't generate libcalls for wide shifts on Windows (PR42711)
Neither libgcc or compiler-rt are usually used on Windows, so these
functions can't be called.
Differential revision: https://reviews.llvm.org/D66880
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/test/CodeGen/AArch64/shift_minsize.ll
llvm/trunk/test/CodeGen/X86/shift_minsize.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Aug 28 06:55:10 2019
@@ -12123,6 +12123,14 @@ bool AArch64TargetLowering::
return X.getValueType().isScalarInteger() || NewShiftOpcode == ISD::SHL;
}
+bool AArch64TargetLowering::shouldExpandShift(SelectionDAG &DAG,
+ SDNode *N) const {
+ if (DAG.getMachineFunction().getFunction().hasMinSize() &&
+ !Subtarget->isTargetWindows())
+ return false;
+ return true;
+}
+
void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
// Update IsSplitCSR in AArch64unctionInfo.
AArch64FunctionInfo *AFI = Entry->getParent()->getInfo<AArch64FunctionInfo>();
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Wed Aug 28 06:55:10 2019
@@ -493,11 +493,7 @@ public:
unsigned OldShiftOpcode, unsigned NewShiftOpcode,
SelectionDAG &DAG) const override;
- bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
- if (DAG.getMachineFunction().getFunction().hasMinSize())
- return false;
- return true;
- }
+ bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
bool shouldTransformSignedTruncationCheck(EVT XVT,
unsigned KeptBits) const override {
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 28 06:55:10 2019
@@ -5104,6 +5104,14 @@ bool X86TargetLowering::shouldFoldMaskTo
return true;
}
+bool X86TargetLowering::shouldExpandShift(SelectionDAG &DAG,
+ SDNode *N) const {
+ if (DAG.getMachineFunction().getFunction().hasMinSize() &&
+ !Subtarget.isOSWindows())
+ return false;
+ return true;
+}
+
bool X86TargetLowering::shouldSplatInsEltVarIndex(EVT VT) const {
// Any legal vector type can be splatted more efficiently than
// loading/spilling from memory.
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Aug 28 06:55:10 2019
@@ -873,11 +873,7 @@ namespace llvm {
return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
}
- bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
- if (DAG.getMachineFunction().getFunction().hasMinSize())
- return false;
- return true;
- }
+ bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
bool shouldSplatInsEltVarIndex(EVT VT) const override;
Modified: llvm/trunk/test/CodeGen/AArch64/shift_minsize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/shift_minsize.ll?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/shift_minsize.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/shift_minsize.ll Wed Aug 28 06:55:10 2019
@@ -1,5 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-windows | FileCheck %s -check-prefix=CHECK-WIN
+
+; The Windows runtime doesn't have these.
+; CHECK-WIN-NOT: __ashlti3
+; CHECK-WIN-NOT: __ashrti3
define i64 @f0(i64 %val, i64 %amt) minsize optsize {
; CHECK-LABEL: f0:
@@ -53,6 +58,7 @@ define dso_local { i64, i64 } @shl128(i6
; CHECK-NEXT: bl __ashlti3
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
+
entry:
%x.sroa.2.0.insert.ext = zext i64 %x.coerce1 to i128
%x.sroa.2.0.insert.shift = shl nuw i128 %x.sroa.2.0.insert.ext, 64
Modified: llvm/trunk/test/CodeGen/X86/shift_minsize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift_minsize.ll?rev=370204&r1=370203&r2=370204&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift_minsize.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift_minsize.ll Wed Aug 28 06:55:10 2019
@@ -1,5 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64--windows-msvc | FileCheck %s -check-prefix=CHECK-WIN
+
+; The Windows runtime doesn't have these.
+; CHECK-WIN-NOT: __ashlti3
+; CHECK-WIN-NOT: __ashrti3
+; CHECK-WIN-NOT: __lshrti3
define i64 @f0(i64 %val, i64 %amt) minsize optsize {
; CHECK-LABEL: f0:
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