[PATCH] D66295: [ARM] Sink add/mul(shufflevector(insertelement(...), ...), ...) for MVE instruction selection

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:14317
+          unsigned Opc = Insn->getOpcode();
+          if (Opc != Instruction::Add && Opc != Instruction::Mul)
+            return false;
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Is it possible to come up with a way to not have to repeat which instructions can be sunk to? Possibly considering things like vsub, which can only be sunk if the operand is the second instruction (although that is not your problem here, it will likely be someones problem soon enough).


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Comment at: llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll:129
+  %wide.load18 = load <4 x i32>, <4 x i32>* %8, align 4
+  %9 = sub nsw <4 x i32> %wide.load18, %broadcast.splat16
+  %10 = getelementptr inbounds i32, i32* %d2, i32 %index
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Can you change this to the first operand of the sub. There is technically an MVE VSUB instruction that takes a grp as the second operand, and I presume eventually we will be looking at making that perform the same trick we have here for add and mul.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66295/new/

https://reviews.llvm.org/D66295