[PATCH] D66805: [MIPS] For vectors, select `add %x, -1` as `sub %x, 1`

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

This patch targets very specific values(1,-1) but there are more. The trick for D62341 <https://reviews.llvm.org/D62341> is that msa vector add/sub imm accept 5 bit unsigned imm, so it is ok to switch from add imm to sub imm (also sub to add) if it changes imm form negative to positive.  I think it is cleanest to have some hook and ask target if it would like to transform sub into add (add to sub) with imm.


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https://reviews.llvm.org/D66805