[PATCH] D66769: [GlobalISel] Import patterns containing SUBREG_TO_REG

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added reviewers: aemerson, dsanders, arsenm, igorb.
Herald added subscribers: Petar.Avramovic, jfb, kristof.beyls, javed.absar, rovka, wdng.
Herald added a project: LLVM.

Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. There are some intrinsic + load/store patterns in AArch64 that use this.

- Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split.

- Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it.

- Update impacted tests in the AArch64 and X86 backends.

This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness.


https://reviews.llvm.org/D66769

Files:
  llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
  llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
  llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
  llvm/test/TableGen/GlobalISelEmitterSubreg.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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