[PATCH] D63973: [MachineVerifier] Improve checks of target instructions operands.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

@kparzysz might be able to help with hexagon failures.

In D63973#1644274 <https://reviews.llvm.org/D63973#1644274>, @jonpa wrote:

> ping!
>
> It would be very nice if people with knowledge of the Hexagon and X86 backends could help out on fixing the failing tests. Note that these tests have been discovered to have a broken MIR (!), so please help...
>
> Here is a condensed output of 'ninja check' with this patch applied:
>
>   Failing Tests (5):
>   LLVM :: CodeGen/Hexagon/expand-condsets-phys-reg.mir
>   LLVM :: CodeGen/Hexagon/sdr-global.mir
>   LLVM :: CodeGen/X86/xray-custom-log.ll
>   LLVM :: CodeGen/X86/xray-typed-event-log.ll
>   LLVM :: DebugInfo/X86/live-debug-vars-discard-invalid.mir
>  
>   ******************** TEST 'LLVM :: CodeGen/Hexagon/expand-condsets-phys-reg.mir' FAILED ********************
>   *** Bad machine code: Expected a register operand. ***
>   - function:    fred
>   - basic block: %bb.0  (0x6071598)
>   - instruction: %1:predregs = C2_cmplt %0:intregs, 10
>   - operand 2:   10
>   LLVM ERROR: Found 1 machine code errors.
>  
>   ******************** TEST 'LLVM :: CodeGen/Hexagon/sdr-global.mir' FAILED ********************
>   *** Bad machine code: Expected a register operand. ***
>   - function:    fred
>   - basic block: %bb.0  (0x6071938)
>   - instruction: %0:doubleregs = A4_combineir 0, @g0
>   - operand 2:   @g0
>   LLVM ERROR: Found 1 machine code errors.
>   FileCheck error: '-' is empty.
>   FileCheck command line:  /home/ijonpan/llvm/build/llvm-dev/bin/FileCheck /home/ijonpan/llvm/llvm-dev/test/CodeGen/Hexagon/sdr-global.mir
>



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