[PATCH] D66708: [X86] Pass v32i16/v64i8 in zmm registers on KNL target.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

gcc and icc pass these types in zmm registers in zmm registers.

This patch implements a quick hack to override the register
type before calling convention handling to one that is legal.
Longer term we might want to do something similar to 256-bit
integer registers on AVX1 where we just split all the operations.

Fixes PR42957


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66708

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/all-ones-vector.ll
  llvm/test/CodeGen/X86/avg-mask.ll
  llvm/test/CodeGen/X86/avg.ll
  llvm/test/CodeGen/X86/avx512-ext.ll
  llvm/test/CodeGen/X86/avx512-insert-extract.ll
  llvm/test/CodeGen/X86/avx512-logic.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/avx512-select.ll
  llvm/test/CodeGen/X86/avx512-trunc.ll
  llvm/test/CodeGen/X86/avx512-vbroadcast.ll
  llvm/test/CodeGen/X86/avx512-vbroadcasti128.ll
  llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll
  llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
  llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
  llvm/test/CodeGen/X86/bitcast-setcc-512.ll
  llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
  llvm/test/CodeGen/X86/build-vector-512.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/fast-isel-nontemporal.ll
  llvm/test/CodeGen/X86/fast-isel-vecload.ll
  llvm/test/CodeGen/X86/kshift.ll
  llvm/test/CodeGen/X86/madd.ll
  llvm/test/CodeGen/X86/masked_store_trunc.ll
  llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
  llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
  llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
  llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
  llvm/test/CodeGen/X86/movmsk-cmp.ll
  llvm/test/CodeGen/X86/nontemporal-loads-2.ll
  llvm/test/CodeGen/X86/nontemporal-loads.ll
  llvm/test/CodeGen/X86/pmul.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
  llvm/test/CodeGen/X86/subvector-broadcast.ll
  llvm/test/CodeGen/X86/var-permute-512.ll
  llvm/test/CodeGen/X86/vec_shift6.ll
  llvm/test/CodeGen/X86/vector-bitreverse.ll
  llvm/test/CodeGen/X86/vector-compare-results.ll
  llvm/test/CodeGen/X86/vector-fshl-512.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
  llvm/test/CodeGen/X86/vector-lzcnt-512.ll
  llvm/test/CodeGen/X86/vector-popcnt-512.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-mul.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
  llvm/test/CodeGen/X86/vector-rotate-512.ll
  llvm/test/CodeGen/X86/vector-sext.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
  llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
  llvm/test/CodeGen/X86/vector-shift-shl-512.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
  llvm/test/CodeGen/X86/vector-shuffle-avx512.ll
  llvm/test/CodeGen/X86/vector-shuffle-v1.ll
  llvm/test/CodeGen/X86/vector-trunc-packus.ll
  llvm/test/CodeGen/X86/vector-trunc-ssat.ll
  llvm/test/CodeGen/X86/vector-trunc-usat.ll
  llvm/test/CodeGen/X86/vector-trunc.ll
  llvm/test/CodeGen/X86/vector-tzcnt-512.ll
  llvm/test/CodeGen/X86/vector-zext.ll
  llvm/test/CodeGen/X86/viabs.ll