[PATCH] D66703: [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: efriedma, simon_tatham, rs, t.p.northover, grosbach.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The code here seems to date back to r134705, when tablegen lowering was first being added. I don't believe that we need to include CPSR implicit operands on the MCInst. This now works more like other backends (like AArch64), where all implicit registers are skipped.

This allows the AliasInst for CSEL's to match correctly, as can be seen in the test changes.


https://reviews.llvm.org/D66703

Files:
  llvm/lib/Target/ARM/ARMMCInstLower.cpp
  llvm/test/CodeGen/Thumb2/csel.ll
  llvm/test/CodeGen/Thumb2/mve-abs.ll
  llvm/test/CodeGen/Thumb2/mve-fmath.ll
  llvm/test/CodeGen/Thumb2/mve-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-pred-and.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
  llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
  llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
  llvm/test/CodeGen/Thumb2/mve-pred-not.ll
  llvm/test/CodeGen/Thumb2/mve-pred-or.ll
  llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
  llvm/test/CodeGen/Thumb2/mve-vcmp.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpz.ll

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