[PATCH] D66687: [x86] try to form more bt/test + set out of shift+mask patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:39006
+  APInt OneBit =
+      APInt::getOneBitSet(VT.getSizeInBits(), Srl.getConstantOperandVal(1));
+  SDValue BitMask = DAG.getConstant(OneBit, DL, VT);
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How do we know the shift amount isn't bigger than the bit width?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66687/new/

https://reviews.llvm.org/D66687