[llvm] r369658 - [PowerPC] Add combined ELF ABI and 32/64 bit queries to the subtarget. [NFC]
Sean Fertile via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 22 08:11:28 PDT 2019
Author: sfertile
Date: Thu Aug 22 08:11:28 2019
New Revision: 369658
URL: http://llvm.org/viewvc/llvm-project?rev=369658&view=rev
Log:
[PowerPC] Add combined ELF ABI and 32/64 bit queries to the subtarget. [NFC]
A lot of places in the code combine checks for both ABI (SVR4/Darwin/AIX) and
addressing mode (64-bit vs 32-bit). In an attempt to make some of the code more
readable I've added a couple functions that combine checking for the ELF abi and
64-bit/32-bit code at once. As we add more AIX support I intend to add similar
functions for the AIX ABI.
Differential Revision: https://reviews.llvm.org/D65814
Modified:
llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
Modified: llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCFastISel.cpp Thu Aug 22 08:11:28 2019
@@ -2464,7 +2464,7 @@ namespace llvm {
const TargetLibraryInfo *LibInfo) {
// Only available on 64-bit ELF for now.
const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
- if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
+ if (Subtarget.is64BitELFABI())
return new PPCFastISel(FuncInfo, LibInfo);
return nullptr;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Aug 22 08:11:28 2019
@@ -5152,8 +5152,8 @@ void PPCDAGToDAGISel::Select(SDNode *N)
}
case PPCISD::PPC32_PICGOT:
// Generate a PIC-safe GOT reference.
- assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
- "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
+ assert(PPCSubTarget->is32BitELFABI() &&
+ "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT,
PPCLowering->getPointerTy(CurDAG->getDataLayout()),
MVT::i32);
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 22 08:11:28 2019
@@ -431,28 +431,26 @@ PPCTargetLowering::PPCTargetLowering(con
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);
- if (Subtarget.isSVR4ABI()) {
- if (isPPC64) {
- // VAARG always uses double-word chunks, so promote anything smaller.
- setOperationAction(ISD::VAARG, MVT::i1, Promote);
- AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
- setOperationAction(ISD::VAARG, MVT::i8, Promote);
- AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
- setOperationAction(ISD::VAARG, MVT::i16, Promote);
- AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
- setOperationAction(ISD::VAARG, MVT::i32, Promote);
- AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
- setOperationAction(ISD::VAARG, MVT::Other, Expand);
- } else {
- // VAARG is custom lowered with the 32-bit SVR4 ABI.
- setOperationAction(ISD::VAARG, MVT::Other, Custom);
- setOperationAction(ISD::VAARG, MVT::i64, Custom);
- }
+ if (Subtarget.is64BitELFABI()) {
+ // VAARG always uses double-word chunks, so promote anything smaller.
+ setOperationAction(ISD::VAARG, MVT::i1, Promote);
+ AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
+ setOperationAction(ISD::VAARG, MVT::i8, Promote);
+ AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
+ setOperationAction(ISD::VAARG, MVT::i16, Promote);
+ AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
+ setOperationAction(ISD::VAARG, MVT::i32, Promote);
+ AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
+ setOperationAction(ISD::VAARG, MVT::Other, Expand);
+ } else if (Subtarget.is32BitELFABI()) {
+ // VAARG is custom lowered with the 32-bit SVR4 ABI.
+ setOperationAction(ISD::VAARG, MVT::Other, Custom);
+ setOperationAction(ISD::VAARG, MVT::i64, Custom);
} else
setOperationAction(ISD::VAARG, MVT::Other, Expand);
- if (Subtarget.isSVR4ABI() && !isPPC64)
- // VACOPY is custom lowered with the 32-bit SVR4 ABI.
+ // VACOPY is custom lowered with the 32-bit SVR4 ABI.
+ if (Subtarget.is32BitELFABI())
setOperationAction(ISD::VACOPY , MVT::Other, Custom);
else
setOperationAction(ISD::VACOPY , MVT::Other, Expand);
@@ -2694,7 +2692,7 @@ SDValue PPCTargetLowering::LowerConstant
// 64-bit SVR4 ABI code is always position-independent.
// The actual address of the GlobalValue is stored in the TOC.
- if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
+ if (Subtarget.is64BitELFABI()) {
setUsesTOCBasePtr(DAG);
SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
return getTOCEntry(DAG, SDLoc(CP), GA);
@@ -2770,7 +2768,7 @@ SDValue PPCTargetLowering::LowerJumpTabl
// 64-bit SVR4 ABI code is always position-independent.
// The actual address of the GlobalValue is stored in the TOC.
- if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
+ if (Subtarget.is64BitELFABI()) {
setUsesTOCBasePtr(DAG);
SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
return getTOCEntry(DAG, SDLoc(JT), GA);
@@ -2799,14 +2797,18 @@ SDValue PPCTargetLowering::LowerBlockAdd
// 64-bit SVR4 ABI code is always position-independent.
// The actual BlockAddress is stored in the TOC.
- if (Subtarget.isSVR4ABI() &&
- (Subtarget.isPPC64() || isPositionIndependent())) {
- if (Subtarget.isPPC64())
- setUsesTOCBasePtr(DAG);
+ if (Subtarget.is64BitELFABI()) {
+ setUsesTOCBasePtr(DAG);
SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
return getTOCEntry(DAG, SDLoc(BASDN), GA);
}
+ // 32-bit position-independent ELF stores the BlockAddress in the .got.
+ if (Subtarget.is32BitELFABI() && isPositionIndependent())
+ return getTOCEntry(
+ DAG, SDLoc(BASDN),
+ DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
+
unsigned MOHiFlag, MOLoFlag;
bool IsPIC = isPositionIndependent();
getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
@@ -2921,7 +2923,7 @@ SDValue PPCTargetLowering::LowerGlobalAd
// 64-bit SVR4 ABI & AIX ABI code is always position-independent.
// The actual address of the GlobalValue is stored in the TOC.
- if ((Subtarget.isSVR4ABI() && Subtarget.isPPC64()) || Subtarget.isAIXABI()) {
+ if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
setUsesTOCBasePtr(DAG);
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
return getTOCEntry(DAG, DL, GA);
@@ -3383,17 +3385,17 @@ SDValue PPCTargetLowering::LowerFormalAr
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
- if (Subtarget.isSVR4ABI()) {
- if (Subtarget.isPPC64())
- return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
- dl, DAG, InVals);
- else
- return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
- dl, DAG, InVals);
- } else {
- return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
- dl, DAG, InVals);
- }
+ if (Subtarget.is64BitELFABI())
+ return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
+ InVals);
+ else if (Subtarget.is32BitELFABI())
+ return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
+ InVals);
+
+ // FIXME: We are using this for both AIX and Darwin. We should add appropriate
+ // AIX testing, and rename it appropriately.
+ return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
+ InVals);
}
SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
@@ -4522,7 +4524,7 @@ callsShareTOCBase(const Function *Caller
static bool
needStackSlotPassParameters(const PPCSubtarget &Subtarget,
const SmallVectorImpl<ISD::OutputArg> &Outs) {
- assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64());
+ assert(Subtarget.is64BitELFABI());
const unsigned PtrByteSize = 8;
const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
@@ -4932,7 +4934,7 @@ PrepareCall(SelectionDAG &DAG, SDValue &
ImmutableCallSite CS, const PPCSubtarget &Subtarget) {
bool isPPC64 = Subtarget.isPPC64();
bool isSVR4ABI = Subtarget.isSVR4ABI();
- bool isELFv2ABI = Subtarget.isELFv2ABI();
+ bool is64BitELFv1ABI = isPPC64 && isSVR4ABI && !Subtarget.isELFv2ABI();
bool isAIXABI = Subtarget.isAIXABI();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
@@ -5003,7 +5005,7 @@ PrepareCall(SelectionDAG &DAG, SDValue &
// to do the call, we can't use PPCISD::CALL.
SDValue MTCTROps[] = {Chain, Callee, InFlag};
- if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
+ if (is64BitELFv1ABI) {
// Function pointers in the 64-bit SVR4 ABI do not point to the function
// entry point, but to the function descriptor (the function entry point
// address is part of the function descriptor though).
@@ -5091,7 +5093,7 @@ PrepareCall(SelectionDAG &DAG, SDValue &
CallOpc = PPCISD::BCTRL;
Callee.setNode(nullptr);
// Add use of X11 (holding environment pointer)
- if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
+ if (is64BitELFv1ABI && !hasNest)
Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
// Add CTR register as callee so a bctr can be emitted later.
if (isTailCall)
@@ -10511,7 +10513,7 @@ PPCTargetLowering::emitEHSjLjSetJmp(Mach
Register LabelReg = MRI.createVirtualRegister(PtrRC);
Register BufReg = MI.getOperand(1).getReg();
- if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
+ if (Subtarget.is64BitELFABI()) {
setUsesTOCBasePtr(*MBB->getParent());
MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
.addReg(PPC::X2)
@@ -10688,7 +10690,7 @@ PPCTargetLowering::EmitInstrWithCustomIn
MachineBasicBlock *BB) const {
if (MI.getOpcode() == TargetOpcode::STACKMAP ||
MI.getOpcode() == TargetOpcode::PATCHPOINT) {
- if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
+ if (Subtarget.is64BitELFABI() &&
MI.getOpcode() == TargetOpcode::PATCHPOINT) {
// Call lowering should have added an r2 operand to indicate a dependence
// on the TOC base pointer value. It can't however, because there is no
@@ -14424,7 +14426,7 @@ unsigned PPCTargetLowering::getRegisterB
bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
// 32-bit SVR4 ABI access everything as got-indirect.
- if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
+ if (Subtarget.is32BitELFABI())
return true;
// AIX accesses everything indirectly through the TOC, which is similar to
@@ -15243,7 +15245,7 @@ SDValue PPCTargetLowering::combineMUL(SD
bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
// Only duplicate to increase tail-calls for the 64bit SysV ABIs.
- if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
+ if (!Subtarget.is64BitELFABI())
return false;
// If not a tail call then no need to proceed.
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Aug 22 08:11:28 2019
@@ -325,13 +325,13 @@ BitVector PPCRegisterInfo::getReservedRe
bool IsPositionIndependent = TM.isPositionIndependent();
if (hasBasePointer(MF)) {
- if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
+ if (Subtarget.is32BitELFABI() && IsPositionIndependent)
markSuperRegs(Reserved, PPC::R29);
else
markSuperRegs(Reserved, PPC::R30);
}
- if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
+ if (Subtarget.is32BitELFABI() && IsPositionIndependent)
markSuperRegs(Reserved, PPC::R30);
// Reserve Altivec registers when Altivec is unavailable.
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Thu Aug 22 08:11:28 2019
@@ -260,8 +260,7 @@ def GPRC : RegisterClass<"PPC", [i32], 3
// put it at the end of the list.
let AltOrders = [(add (sub GPRC, R2), R2)];
let AltOrderSelect = [{
- const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
- return S.isPPC64() && S.isSVR4ABI();
+ return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}];
}
@@ -272,8 +271,7 @@ def G8RC : RegisterClass<"PPC", [i64], 6
// put it at the end of the list.
let AltOrders = [(add (sub G8RC, X2), X2)];
let AltOrderSelect = [{
- const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
- return S.isPPC64() && S.isSVR4ABI();
+ return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}];
}
@@ -285,8 +283,7 @@ def GPRC_NOR0 : RegisterClass<"PPC", [i3
// put it at the end of the list.
let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
let AltOrderSelect = [{
- const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
- return S.isPPC64() && S.isSVR4ABI();
+ return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}];
}
@@ -295,8 +292,7 @@ def G8RC_NOX0 : RegisterClass<"PPC", [i6
// put it at the end of the list.
let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
let AltOrderSelect = [{
- const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>();
- return S.isPPC64() && S.isSVR4ABI();
+ return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}];
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=369658&r1=369657&r2=369658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Thu Aug 22 08:11:28 2019
@@ -320,6 +320,9 @@ public:
bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); }
bool isELFv2ABI() const;
+ bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
+ bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
+
/// Originally, this function return hasISEL(). Now we always enable it,
/// but may expand the ISEL instruction later.
bool enableEarlyIfConversion() const override { return true; }
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