[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D66571#1640759 <https://reviews.llvm.org/D66571#1640759>, @RKSimon wrote:

> We already have these in TLI:
>
>   TLI::shouldFoldConstantShiftPairToMask
>   TLI::shouldFoldMaskToVariableShiftPair
>
>
> ideally we'd keep everything in DAGCombine and have a suitable set of TLI hooks to indicate what codegen we prefer


+1 to that, this was the patch i was going to look into after D62100 <https://reviews.llvm.org/D62100> but that one got stuck.
Which means, this doesn't really have to be X86-specific.


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