[PATCH] D66479: [RISCV] Add LLVM intrinsics for the Bit Manipulation extension

Dávid Bolvanský via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 21 03:31:58 PDT 2019


xbolva00 added subscribers: spatel, xbolva00.
xbolva00 added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:99
+
+def int_riscv_bmatflip : BitmanipGprIntrinsic;
+
----------------
s.egerton wrote:
> I haven't added intrinsics for every new instruction. Either because they are too simple (andn, orn, xnor, min and max) or because there is already an IR intrinsic that has the same function (clz, ctz, pcnt, ror, rol, fsl and fsr).
> Are there any other IR intrinsics that it would be better to remove?
InstCombine could benefit from smin/smax/umin/umax intrinsic

@spatel ?


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  https://reviews.llvm.org/D66479/new/

https://reviews.llvm.org/D66479





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