[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 17:40:00 PDT 2019
craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon, lebedev.ri, andreadb.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
If we're already shifting right we can trade the AND for a SHL to clear out the upper bits before the shift right. This can avoid a constant pool on the AND.
This patch doesn't currently work for AND's with power 2 since those get turned into shuffles and only become ANDs again during the last lowering step. At which point the mask is in a constant pool. We can probably look through the constant pool to fix this, but I haven't looked at that yet.
https://reviews.llvm.org/D66571
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-lshr-and.ll
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