[PATCH] D66515: [MVT] Add v16f16 and v32f16 vectors.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

LGTM but @arsenm needs to confirm



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Comment at: llvm/include/llvm/CodeGen/ValueTypes.td:165
+def FlagVT : ValueType<0  , 130>;   // Pre-RA sched glue
+def isVoid : ValueType<0  , 131>;   // Produces no value
+def untyped: ValueType<8  , 132>;   // Produces an untyped value
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craig.topper wrote:
> RKSimon wrote:
> > Would it not make sense to have a comment here about keeping isVoid in sync with llvm/test/TableGen/intrinsic-varargs.td ?
> Or we just move this file to Support and include it in the test....
SGTM :-)


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:161
+  setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
+  setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
 
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craig.topper wrote:
> RKSimon wrote:
> > Do these have test coverage already?
> > 
> > Do these need to be part of this patch or should they be in a followup?
> I got isel errors without these lines. The default is Legal for all types. So we need to explicitly disable extloads for any legal result type. X86 does this with a generic loop and selectively reenables.
OK I'll leave this to @arsenm


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