[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/machineoutliner.ll:1
+; RUN: llc -march riscv32 < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -march riscv32 -enable-machine-outliner < %s \
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I recommend writing a .mir test for this instead of a .ll test. (e.g, use -stop-before=machine-outliner -simplify-mir)

That would make the test resilient against other code generation changes, and make it easier to test the instruction sequences you want to test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210