[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill marked 2 inline comments as done.
lewis-revill added inline comments.
Herald added a subscriber: pzheng.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:481
+  RS.enterBasicBlock(MBB);
+  return !RS.isRegUsed(RISCV::X5);
+}
----------------
luismarques wrote:
> If we are only going to support one possible register for now, shouldn't it be the one least likely to already be in use? Wouldn't that be t6 (x31)?
That's a sensible suggestion, I was using t0 to match how the save/restore libcalls behave so I presumed there was a good reason for using t0. Don't we also need to think about RV32E here though?




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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:503
+
+  // RISCV::PseudoRET = 8 bytes.
+  unsigned FrameOverhead = 8;
----------------
efriedma wrote:
> > RISCV::PseudoRET = 8 bytes.
> 
> I don't understand the math here.
Good catch this is definitely an error.


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https://reviews.llvm.org/D66210