[llvm] r369512 - [MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 02:43:20 PDT 2019
Author: petar.avramovic
Date: Wed Aug 21 02:43:20 2019
New Revision: 369512
URL: http://llvm.org/viewvc/llvm-project?rev=369512&view=rev
Log:
[MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
NarrowScalar G_ZEXTLOAD and G_SEXTLOAD to s32 for MIPS32.
Differential Revision: https://reviews.llvm.org/D66205
Modified:
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=369512&r1=369511&r2=369512&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Wed Aug 21 02:43:20 2019
@@ -50,9 +50,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
.legalFor({{s64, s32}});
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
- .legalForTypesWithMemDesc({{s32, p0, 8, 8},
- {s32, p0, 16, 8}})
- .minScalar(0, s32);
+ .legalForTypesWithMemDesc({{s32, p0, 8, 8},
+ {s32, p0, 16, 8}})
+ .clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
.legalIf([](const LegalityQuery &Query) { return false; })
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir?rev=369512&r1=369511&r2=369512&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir Wed Aug 21 02:43:20 2019
@@ -6,10 +6,12 @@
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
...
---
@@ -95,6 +97,32 @@ body: |
...
---
+name: load4_s32_to_zextLoad4_s64
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[C]](s32)
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
+---
name: load1_s8_to_sextLoad1_s32
alignment: 2
tracksRegLiveness: true
@@ -176,3 +204,32 @@ body: |
RetRA implicit $v0
...
+---
+name: load4_s32_to_sextLoad4_s64
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
+ ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32)
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll?rev=369512&r1=369511&r2=369512&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll Wed Aug 21 02:43:20 2019
@@ -49,6 +49,19 @@ entry:
ret i16 %conv
}
+define i64 @load4_s32_to_zextLoad4_s64(i32* %px) {
+; MIPS32-LABEL: load4_s32_to_zextLoad4_s64:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lw $2, 0($4)
+; MIPS32-NEXT: ori $3, $zero, 0
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i32, i32* %px
+ %conv = zext i32 %0 to i64
+ ret i64 %conv
+}
+
define i32 @load1_s8_to_sextLoad1_s32(i8* %px) {
; MIPS32-LABEL: load1_s8_to_sextLoad1_s32:
; MIPS32: # %bb.0: # %entry
@@ -96,3 +109,18 @@ entry:
%conv = sext i8 %0 to i16
ret i16 %conv
}
+
+define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
+; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lw $1, 0($4)
+; MIPS32-NEXT: ori $2, $zero, 31
+; MIPS32-NEXT: srav $3, $1, $2
+; MIPS32-NEXT: move $2, $1
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = load i32, i32* %px
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir?rev=369512&r1=369511&r2=369512&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir Wed Aug 21 02:43:20 2019
@@ -6,10 +6,12 @@
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
+ define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
...
---
@@ -100,6 +102,31 @@ body: |
...
---
+name: load4_s32_to_zextLoad4_s64
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+ %2:_(s64) = G_ZEXT %1(s32)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
+---
name: load1_s8_to_sextLoad1_s32
alignment: 2
tracksRegLiveness: true
@@ -186,3 +213,28 @@ body: |
RetRA implicit $v0
...
+---
+name: load4_s32_to_sextLoad4_s64
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
+ ; MIPS32: $v0 = COPY [[UV]](s32)
+ ; MIPS32: $v1 = COPY [[UV1]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+ %2:_(s64) = G_SEXT %1(s32)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir?rev=369512&r1=369511&r2=369512&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir Wed Aug 21 02:43:20 2019
@@ -4,8 +4,10 @@
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
+ define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
+ define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
...
---
@@ -51,6 +53,33 @@ body: |
...
---
+name: load4_s32_to_zextLoad4_s64
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: $v1 = COPY [[C]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+ %6:_(s32) = G_CONSTANT i32 0
+ %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
+---
name: load1_s8_to_sextLoad1_s32
alignment: 2
legalized: true
@@ -92,3 +121,37 @@ body: |
RetRA implicit $v0
...
+---
+name: load4_s32_to_sextLoad4_s64
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0
+
+ ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+ ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
+ ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
+ ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32: $v1 = COPY [[ASHR]](s32)
+ ; MIPS32: RetRA implicit $v0, implicit $v1
+ %0:_(p0) = COPY $a0
+ %5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
+ %9:_(s32) = G_CONSTANT i32 31
+ %10:_(s32) = G_CONSTANT i32 0
+ %8:_(s32) = COPY %9(s32)
+ %7:_(s32) = G_ASHR %5, %8(s32)
+ %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
+ %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
+ $v0 = COPY %3(s32)
+ $v1 = COPY %4(s32)
+ RetRA implicit $v0, implicit $v1
+
+...
+
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