[llvm] r369476 - gn build: Merge r369467
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 20 16:49:12 PDT 2019
Author: nico
Date: Tue Aug 20 16:49:12 2019
New Revision: 369476
URL: http://llvm.org/viewvc/llvm-project?rev=369476&view=rev
Log:
gn build: Merge r369467
Modified:
llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Modified: llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn?rev=369476&r1=369475&r2=369476&view=diff
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn (original)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn Tue Aug 20 16:49:12 2019
@@ -20,17 +20,31 @@ tablegen("RISCVGenDAGISel") {
td_file = "RISCV.td"
}
+tablegen("RISCVGenGlobalISel") {
+ visibility = [ ":LLVMRISCVCodeGen" ]
+ args = [ "-gen-global-isel" ]
+ td_file = "RISCV.td"
+}
+
tablegen("RISCVGenMCPseudoLowering") {
visibility = [ ":LLVMRISCVCodeGen" ]
args = [ "-gen-pseudo-lowering" ]
td_file = "RISCV.td"
}
+tablegen("RISCVGenRegisterBank") {
+ visibility = [ ":LLVMRISCVCodeGen" ]
+ args = [ "-gen-register-bank" ]
+ td_file = "RISCV.td"
+}
+
static_library("LLVMRISCVCodeGen") {
deps = [
":RISCVGenCompressInstEmitter",
":RISCVGenDAGISel",
+ ":RISCVGenGlobalISel",
":RISCVGenMCPseudoLowering",
+ ":RISCVGenRegisterBank",
"MCTargetDesc",
"TargetInfo",
"Utils",
@@ -46,13 +60,17 @@ static_library("LLVMRISCVCodeGen") {
include_dirs = [ "." ]
sources = [
"RISCVAsmPrinter.cpp",
+ "RISCVCallLowering.cpp",
"RISCVExpandPseudoInsts.cpp",
"RISCVFrameLowering.cpp",
"RISCVISelDAGToDAG.cpp",
"RISCVISelLowering.cpp",
"RISCVInstrInfo.cpp",
+ "RISCVInstructionSelector.cpp",
+ "RISCVLegalizerInfo.cpp",
"RISCVMCInstLower.cpp",
"RISCVMergeBaseOffset.cpp",
+ "RISCVRegisterBankInfo.cpp",
"RISCVRegisterInfo.cpp",
"RISCVSubtarget.cpp",
"RISCVTargetMachine.cpp",
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