[PATCH] D66498: [GlobalISel] Import patterns containing INSERT_SUBREG

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added reviewers: dsanders, aemerson, arsenm, igorb.
Herald added subscribers: Petar.Avramovic, mgrang, hiraditya, kristof.beyls, javed.absar, rovka, wdng.
Herald added a project: LLVM.

This teaches the importer to handle INSERT_SUBREG instructions. We were missing patterns involving INSERT_SUBREG in AArch64.

To meaningfully import it, the GlobalISelEmitter needs to know how to infer a super register class for a given register class.

This patch introduces the following to achieve this:

- `getSuperRegForSubReg`, a function which finds the largest register class which supports a value type and subregister index
- `inferSuperRegisterClass`, a function which finds the appropriate super register class for an INSERT_SUBREG
- `inferRegClassFromPattern`, a function which allows for some trivial lookthrough into instructions
- `getRegClassFromLeaf`, a helper function which returns the register class for a leaf `TreePatternNode`
- Support for subregister index operands in `importExplicitUseRenderer`

It also

- Updates tests in each backend which are impacted by the change
- Adds GlobalISelEmitterInsertSubreg.td to test that we import and skip the expected patterns

As a result of this patch, INSERT_SUBREG patterns in X86 may use the LOW32_ADDR_ACCESS_RBP register class instead of GR32. This is correct, since the register class contains the same registers as GR32 (except with the addition of RBP). So, this also teaches X86 to handle that register class. This is in line with X86ISelLowering, which treats this as a GR class.


https://reviews.llvm.org/D66498

Files:
  llvm/lib/Target/X86/X86RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
  llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
  llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
  llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
  llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
  llvm/test/TableGen/GlobalISelEmitterInsertSubreg.td
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/CodeGenTarget.h
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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