[PATCH] D66456: [DAGCombiner][X86] Teach visitCONCAT_VECTORS to combine (concat_vectors (concat_vectors X, Y), undef)) -> (concat_vectors X, Y, undef, undef)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:43259
     // subvector into a zero vector.
-    if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 &&
+    if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
         isNullConstant(SubVec.getOperand(1)) &&
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Are we sure that this works in the general IdxVal case?


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Comment at: llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll:7593
 ; NoVLX-NEXT:    kmovw %k0, %eax
-; NoVLX-NEXT:    andl $3, %eax
+; NoVLX-NEXT:    movzbl %al, %eax
 ; NoVLX-NEXT:    vzeroupper
----------------
This looks like we're missing a computeKnownBitsForTargetNode handling for a X86ISD opcode?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66456/new/

https://reviews.llvm.org/D66456