[PATCH] D65542: [PeepholeOptimizer] Don't assume bitcast def always has input

[Jinsong Ji via Phabricator via llvm-commits]

jsji updated this revision to Diff 215647.
jsji added a comment.

Update the MIR test using script.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65542/new/

https://reviews.llvm.org/D65542

Files:
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/bitcast-peephole.mir


Index: llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/bitcast-peephole.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=powerpc64le-linux-gnu -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name:            bitCast
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: bitCast
+    ; CHECK: [[XXLEQVOnes:%[0-9]+]]:vsrc = XXLEQVOnes
+    ; CHECK: $v2 = COPY [[XXLEQVOnes]]
+    ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $v2
+    %0:vsrc = XXLEQVOnes
+    $v2 = COPY %0
+    BLR8 implicit $lr8, implicit $rm, implicit $v2
+
+...
+
+# This used to hit an assertion:
+#   llvm/include/llvm/CodeGen/MachineInstr.h:417: const
+#   llvm::MachineOperand &llvm::MachineInstr::getOperand(unsigned int)
+#   const: Assertion `i < getNumOperands() && "getOperand() out of range!"' failed.
+#
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1314,7 +1314,7 @@
       isReMaterializable = 1 in {
     def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
                          "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
-                         [(set v4i32:$XT, (v4i32 immAllOnesV))]>;
+                         [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>;
   }
 
   def XXLORC : XX3Form<60, 170,
@@ -4103,8 +4103,6 @@
   }
 
   let Predicates = [HasP8Vector] in {
-    def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
-              (XXLEQVOnes)>;
     def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
               (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
     def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
Index: llvm/lib/CodeGen/PeepholeOptimizer.cpp
===================================================================
--- llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1853,6 +1853,11 @@
     SrcIdx = OpIdx;
   }
 
+  // In some rare case, Def has no input, SrcIdx is out of bound,
+  // getOperand(SrcIdx) will fail below.
+  if (SrcIdx >= Def->getNumOperands())
+    return ValueTrackerResult();
+
   // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY
   // will break the assumed guarantees for the upper bits.
   for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {


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