[PATCH] D65931: [AArch64][SVE] Implement abs and neg intrinsics

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

@greened sorry for the delayed response, thanks for taking a look at this.



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Comment at: include/llvm/IR/IntrinsicsAArch64.td:756
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+  class AdvSIMD_Merged1VectorArg_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty],
----------------
greened wrote:
> What does "AdvSIMD" reference?  Why not "SVE?"
`AdvSIMD` is NEON, some of the existing `AdvSIMD` patterns worked fine for our needs (and some of the new ones weren't exactly SVE specific) so we kept the naming scheme. The SVE specific intrinsics we have downstream are prefixed with `AdvSIMD_SVE`. Happy to change this if it's confusing.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65931/new/

https://reviews.llvm.org/D65931