[PATCH] D66228: [mips] Fix 64-bit address loading in case of applying 32-bit mask to the result

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

@sdardis  What is the difference between MipsHi and  MipsLo SD nodes? Some of their patterns are the same, e.g. :

  def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
                (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
  
  def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))),
                (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;

Both act like "glue" between add/shift/nothing node and  node with part of the address (controlled by target flag) and are used for pattern match into lui or addiu.
They are used interchangeably but I didnt find any comments about what these nodes actually do.
MipsHi can be alone (lui) or used in combine with add (into addiu) according to patterns. By the name I would use MipsLo if I wanted it to combine with add into addiu, not MipsHi. 
Aren't all of the MipsHighest, MipsHigher, MipsHi and MipsLo equivalent to some Mips16bitImm node
that would have patterns
Mips16bitImm + shl 16 -> lui
Mips16bitImm + add -> addiu
Mips16bitImm alone -> addiu with zero
but then instead of using MipsHi and MipsHighest alone and expecting lui to be selected we need to make two nodes: Mips16bitImm and shl 16.
MipsHigher and MipsLo are fine if we just replace them with Mips16bitImm.
What difference does SYM_32/SYM_64 make, all selected instructions use only 16 bits of something that is resolved later?


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https://reviews.llvm.org/D66228