[llvm] r368981 - [ARM] MVE trunc to i1 vectors

[David Green via llvm-commits]

Author: dmgreen
Date: Thu Aug 15 02:26:51 2019
New Revision: 368981

URL: http://llvm.org/viewvc/llvm-project?rev=368981&view=rev
Log:
[ARM] MVE trunc to i1 vectors

This adds patterns for selecting trunc instructions from full vectors to i1's
vectors.

Differential Revision: https://reviews.llvm.org/D66201

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
    llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=368981&r1=368980&r2=368981&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Thu Aug 15 02:26:51 2019
@@ -4666,6 +4666,13 @@ let Predicates = [HasMVEInt] in {
             (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), 0, VCCR:$pred))>;
   def : Pat<(v4i32 (anyext  (v4i1  VCCR:$pred))),
             (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), 0, VCCR:$pred))>;
+
+  def : Pat<(v16i1 (trunc (v16i8 MQPR:$v1))),
+            (v16i1 (MVE_VCMPi32r (v16i8 MQPR:$v1), ZR, 1))>;
+  def : Pat<(v8i1 (trunc (v8i16  MQPR:$v1))),
+            (v8i1 (MVE_VCMPi32r (v8i16 MQPR:$v1), ZR, 1))>;
+  def : Pat<(v4i1 (trunc (v4i32  MQPR:$v1))),
+            (v4i1 (MVE_VCMPi32r (v4i32 MQPR:$v1), ZR, 1))>;
 }
 
 let Predicates = [HasMVEFloat] in {

Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll?rev=368981&r1=368980&r2=368981&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll Thu Aug 15 02:26:51 2019
@@ -163,6 +163,67 @@ entry:
 }
 
 
+define arm_aapcs_vfpcc <4 x i32> @trunc_v4i1_v4i32(<4 x i32> %src) {
+; CHECK-LABEL: trunc_v4i1_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vcmp.i32 ne, q0, zr
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = trunc <4 x i32> %src to <4 x i1>
+  %1 = select <4 x i1> %0, <4 x i32> %src, <4 x i32> zeroinitializer
+  ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @trunc_v8i1_v8i16(<8 x i16> %src) {
+; CHECK-LABEL: trunc_v8i1_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vcmp.i32 ne, q0, zr
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = trunc <8 x i16> %src to <8 x i1>
+  %1 = select <8 x i1> %0, <8 x i16> %src, <8 x i16> zeroinitializer
+  ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @trunc_v16i1_v16i8(<16 x i8> %src) {
+; CHECK-LABEL: trunc_v16i1_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vcmp.i32 ne, q0, zr
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = trunc <16 x i8> %src to <16 x i1>
+  %1 = select <16 x i1> %0, <16 x i8> %src, <16 x i8> zeroinitializer
+  ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @trunc_v2i1_v2i64(<2 x i64> %src) {
+; CHECK-LABEL: trunc_v2i1_v2i64:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov r1, s0
+; CHECK-NEXT:    vmov r0, s2
+; CHECK-NEXT:    and r1, r1, #1
+; CHECK-NEXT:    rsbs r1, r1, #0
+; CHECK-NEXT:    and r0, r0, #1
+; CHECK-NEXT:    vmov.32 q1[0], r1
+; CHECK-NEXT:    rsbs r0, r0, #0
+; CHECK-NEXT:    vmov.32 q1[1], r1
+; CHECK-NEXT:    vmov.32 q1[2], r0
+; CHECK-NEXT:    vmov.32 q1[3], r0
+; CHECK-NEXT:    vand q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = trunc <2 x i64> %src to <2 x i1>
+  %1 = select <2 x i1> %0, <2 x i64> %src, <2 x i64> zeroinitializer
+  ret <2 x i64> %1
+}
+
+
 define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {
 ; CHECK-LABEL: uitofp_v4i1_v4f32:
 ; CHECK:       @ %bb.0: @ %entry