[PATCH] D66236: [SDAG][x86] check for relaxed math when matching an FP reduction

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked 2 inline comments as done.
spatel added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:9051
   // <1,u,u,u,u,u,u,u>
+  unsigned Stages = Log2_32(Op.getValueType().getVectorNumElements());
   SDValue PrevOp;
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lebedev.ri wrote:
> precommit?
Yes, will do.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:35487
 
   unsigned HorizOpcode = Opc == ISD::ADD ? X86ISD::HADD : X86ISD::FHADD;
 
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craig.topper wrote:
> So was the FP part of this just unusable before now?
Yes - afaict, we put in the ability for FP down here, but there's no way that was getting down here without matching the reduction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66236/new/

https://reviews.llvm.org/D66236