[PATCH] D66228: [mips] Fix 64-bit address loading in case of applying 32-bit mask to the result

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan created this revision.
atanasyan added reviewers: Petar.Avramovic, sdardis.
Herald added subscribers: jrtc27, hiraditya, arichardson.
Herald added a project: LLVM.

If result of 64-bit address loading combines with 32-bit mask, LLVM tries to optimize the code and remove "redundant" loading of upper 32-bits of the address. It leads to incorrect code on MIPS64 targets.

MIPS backend creates the following chain of commands to load 64-bit address in the `MipsTargetLowering::getAddrNonPICSym64` method:

  (add (shl (add (shl (add %highest(sym), %higher(sym)),
                      16),
                 %hi(sym)),
            16),
       %lo(%sym))

If the mask presents, LLVM decides to optimize the chain of commands. It really does not make sense to load upper 32-bits because the 0x0fffffff mask anyway clears them. So "unnecessary" commands removed and we get this chain:

  (add (shl (%hi(sym), 16), %lo(%sym))

As a result we get incorrect set of instructions with unnecessary 16-bit left shifting:

  lui     at,0x0
      R_MIPS_HI16     foo
  dsll    at,at,0x10
  daddiu  at,at,0
      R_MIPS_LO16     foo

This patch adds patterns which lower `shl (%hi(sym), 16)` code into the single `lui` instruction.

Fix PR42736.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66228

Files:
  llvm/lib/Target/Mips/Mips64InstrInfo.td
  llvm/test/CodeGen/Mips/global-address-with-mask.ll


Index: llvm/test/CodeGen/Mips/global-address-with-mask.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Mips/global-address-with-mask.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=mips64-linux-gnuabi64 \
+; RUN:     -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -mtriple=mips64-linux-gnuabi64 \
+; RUN:     -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC
+
+define void @bar() nounwind {
+entry:
+; PIC:      lui  $[[R0:[0-9]+]], 4095
+; PIC-NEXT: ori  $[[R0]], $[[R0]], 65535
+; PIC-NEXT: ld   $[[R1:[0-9]+]], %got_disp(foo)(${{[0-9]+}})
+; PIC-NEXT: and  $[[R1]], $[[R1]], $[[R0]]
+; PIC-NEXT: sd   $[[R1]]
+
+; STATIC:      lui     $[[R0:[0-9]+]], 4095
+; STATIC-NEXT: ori     $[[R0]], $[[R0]], 65535
+; STATIC-NEXT: lui     $[[R1:[0-9]+]], %hi(foo)
+; STATIC-NEXT: daddiu  $[[R1]], $[[R1]], %lo(foo)
+; STATIC-NEXT: and     $[[R0]], $[[R1]], $[[R0]]
+; STATIC-NEXT: sd      $[[R0]]
+
+  %val = alloca i64, align 8
+  store i64 and (i64 ptrtoint (void ()* @foo to i64), i64 268435455), i64* %val, align 8
+  %0 = load i64, i64* %val, align 8
+  ret void
+}
+
+declare void @foo()
Index: llvm/lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -683,6 +683,15 @@
   def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))),
                 (DADDiu GPR64:$hi, tconstpool:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
 
+  def : MipsPat<(shl (MipsHi (i64 tglobaladdr:$in)), (i32 16)),
+                (LUi64 tglobaladdr:$in)>, ISA_MIPS3, GPR_64;
+  def : MipsPat<(shl (MipsHi (i64 tblockaddress:$in)), (i32 16)),
+                (LUi64 tblockaddress:$in)>, ISA_MIPS3, GPR_64;
+  def : MipsPat<(shl (MipsHi (i64 tjumptable:$in)), (i32 16)),
+                (LUi64 tjumptable:$in)>, ISA_MIPS3, GPR_64;
+  def : MipsPat<(shl (MipsHi (i64 tconstpool:$in)), (i32 16)),
+                (LUi64 tconstpool:$in)>, ISA_MIPS3, GPR_64;
+
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))),
                 (DADDiu GPR64:$hi, tglobaladdr:$lo)>, ISA_MIPS3, GPR_64, SYM_64;
   def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))),


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