[PATCH] D66218: [WebAssembly] Lower SIMD shifts since they are fixed in V8

[Brion Vibber via Phabricator via llvm-commits]

bvibber created this revision.
Herald added subscribers: llvm-commits, sunfish, aheejin, hiraditya, jgravelle-google, sbc100, dschuff.
Herald added a project: LLVM.

Reapply https://reviews.llvm.org/D58800 since V8 has fixed this
in https://chromium-review.googlesource.com/c/v8/v8/+/1722198


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D66218

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp


Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1449,11 +1449,6 @@
   // Only manually lower vector shifts
   assert(Op.getSimpleValueType().isVector());
 
-  // Expand all vector shifts until V8 fixes its implementation
-  // TODO: remove this once V8 is fixed
-  if (!Subtarget->hasUnimplementedSIMD128())
-    return unrollVectorShift(Op, DAG);
-
   // Unroll non-splat vector shifts
   BuildVectorSDNode *ShiftVec;
   SDValue SplatVal;


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