[PATCH] D66184: [AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 13 15:52:07 PDT 2019
aemerson created this revision.
aemerson added a reviewer: paquette.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.
The destinations should be FPRs (for now).
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D66184
Files:
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
Index: llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
@@ -24,3 +24,27 @@
RET_ReallyLR implicit $x0
...
+---
+name: unmerge_s128
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+body: |
+ bb.0:
+ liveins: $q0
+
+ ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
+ ; CHECK-LABEL: name: unmerge_s128
+ ; CHECK: liveins: $q0
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
+ ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK: $x0 = COPY [[UV]](s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %0:_(s128) = COPY $q0
+ %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...
Index: llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -768,7 +768,7 @@
LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
// UNMERGE into scalars from a vector should always use FPR.
// Likewise if any of the uses are FP instructions.
- if (SrcTy.isVector() ||
+ if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
[&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
// Set the register bank of every operand to FPR.
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