[PATCH] D66171: [GlobalISel]: Fix lowering of G_SHUFFLE_VECTOR with scalar sources

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar created this revision.
aditya_nandakumar added reviewers: arsenm, dsanders, aemerson, paquette.
Herald added subscribers: Petar.Avramovic, volkan, hiraditya, rovka, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

We need to handle scalar sources (1 element vector) correctly while lowering.


Repository:
  rL LLVM

https://reviews.llvm.org/D66171

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/MachineVerifier/test_g_shuffle_vector.mir


Index: llvm/test/MachineVerifier/test_g_shuffle_vector.mir
===================================================================
--- llvm/test/MachineVerifier/test_g_shuffle_vector.mir
+++ llvm/test/MachineVerifier/test_g_shuffle_vector.mir
@@ -52,4 +52,8 @@
     ; CHECK: Bad machine code: G_SHUFFLE_VECTOR cannot change element type
     %21:_(s16) = G_SHUFFLE_VECTOR %3, %4, shufflemask(0)
 
+    ; CHECK: Bad machine code: Out of bounds shuffle index
+    %22:_(s32) = G_IMPLICIT_DEF
+    %20:_(<2 x s32>) = G_SHUFFLE_VECTOR %22, %22, shufflemask(0, 2)
+
 ...
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
@@ -1,6 +1,26 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
 
+---
+name: shufflevector_scalar_src
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: shufflevector_scalar_src
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(<2 x s32>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 1)
+    $vgpr0_vgpr1 = COPY %2
+
+...
 ---
 name: shufflevector_v2s32_0_1
 tracksRegLiveness: true
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3821,6 +3821,7 @@
   Register DstReg = MI.getOperand(0).getReg();
   Register Src0Reg = MI.getOperand(1).getReg();
   Register Src1Reg = MI.getOperand(2).getReg();
+  LLT Src0Ty = MRI.getType(Src0Reg);
   LLT DstTy = MRI.getType(DstReg);
   LLT EltTy = DstTy.getElementType();
   int NumElts = DstTy.getNumElements();
@@ -3842,11 +3843,15 @@
       continue;
     }
 
-    Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
-    int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
-    auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
-    auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
-    BuildVec.push_back(Extract.getReg(0));
+    if (Src0Ty.isScalar()) {
+      BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
+    } else {
+      Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
+      int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
+      auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
+      auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
+      BuildVec.push_back(Extract.getReg(0));
+    }
   }
 
   MIRBuilder.buildBuildVector(DstReg, BuildVec);


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