[PATCH] D66163: [AArch64][GlobalISel] Select patterns which use shifted register operands

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

This adds GlobalISel equivalents for the following from AArch64InstrFormats:

- arith_shifted_reg32
- arith_shifted_reg64

And partial support for

- logical_shifted_reg32
- logical_shifted_reg32

The only thing missing for the logical cases is support for rotates. Other than the missing support, the transformation is identical for the arithmetic shifted register and the logical shifted register.

Lots of tests here:

- Add select-arith-shifted-reg.mir to show that we correctly select add and

sub instructions which use this pattern.

- Add select-logical-shifted-reg.mir to cover patterns which are not shared

between the arithmetic and logical cases.

- Update addsub-shifted.ll to show that we correctly fold shifts into

adds/subs.

- Update eon.ll to show that we can select the eon instruction by folding xors.


https://reviews.llvm.org/D66163

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir
  llvm/test/CodeGen/AArch64/addsub-shifted.ll
  llvm/test/CodeGen/AArch64/eon.ll

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