[llvm] r368711 - [ARM] Fix encoding of APSR in CLRM instruction

[Momchil Velikov via llvm-commits]

Author: chill
Date: Tue Aug 13 09:12:46 2019
New Revision: 368711

URL: http://llvm.org/viewvc/llvm-project?rev=368711&view=rev
Log:
[ARM] Fix encoding of APSR in CLRM instruction

The APSR is encoded by setting bit 15 in the register list of the CLRM
instruction (cf. https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf).

Differential Revision: https://reviews.llvm.org/D65873

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
    llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
    llvm/trunk/test/MC/ARM/clrm-asm.s

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=368711&r1=368710&r2=368711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Aug 13 09:12:46 2019
@@ -180,7 +180,7 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>;
 // models the APSR when it's accessed by some special instructions. In such cases
 // it has the same encoding as PC.
 def CPSR       : ARMReg<0,  "cpsr">;
-def APSR       : ARMReg<1,  "apsr">;
+def APSR       : ARMReg<15, "apsr">;
 def APSR_NZCV  : ARMReg<15, "apsr_nzcv">;
 def SPSR       : ARMReg<2,  "spsr">;
 def FPSCR      : ARMReg<3,  "fpscr">;

Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=368711&r1=368710&r2=368711&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Tue Aug 13 09:12:46 2019
@@ -1720,7 +1720,6 @@ getRegisterListOpValue(const MCInst &MI,
   unsigned Reg = MI.getOperand(Op).getReg();
   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
-  bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
 
   unsigned Binary = 0;
 
@@ -1739,21 +1738,13 @@ getRegisterListOpValue(const MCInst &MI,
       Binary |= NumRegs * 2;
   } else {
     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
-    if (!CLRMRegs) {
-      assert(std::is_sorted(MI.begin() + Op, MI.end(),
-                            [&](const MCOperand &LHS, const MCOperand &RHS) {
-                              return MRI.getEncodingValue(LHS.getReg()) <
-                                     MRI.getEncodingValue(RHS.getReg());
-                            }));
-    }
-
+    assert(std::is_sorted(MI.begin() + Op, MI.end(),
+                          [&](const MCOperand &LHS, const MCOperand &RHS) {
+                            return MRI.getEncodingValue(LHS.getReg()) <
+                              MRI.getEncodingValue(RHS.getReg());
+                          }));
     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
-      unsigned RegNo;
-      if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
-        RegNo = 15;
-      } else {
-        RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
-      }
+      unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
       Binary |= 1 << RegNo;
     }
   }

Modified: llvm/trunk/test/MC/ARM/clrm-asm.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/clrm-asm.s?rev=368711&r1=368710&r2=368711&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/clrm-asm.s (original)
+++ llvm/trunk/test/MC/ARM/clrm-asm.s Tue Aug 13 09:12:46 2019
@@ -9,13 +9,16 @@ clrm {r0, r1, r2, r3}
 // ERROR-NOT: register list not in ascending order
 clrm {r3, r4, r1, r2}
 
-// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @ encoding: [0x9f,0xe8,0xff,0xdf]
+// CHECK: clrm            {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} @ encoding: [0x9f,0xe8,0xff,0xdf]
 clrm {r0-r12, lr, apsr}
 
-// CHECK: clrm            {apsr, lr} @ encoding: [0x9f,0xe8,0x00,0xc0]
+// CHECK: clrm            {lr, apsr} @ encoding: [0x9f,0xe8,0x00,0xc0]
 clrm {apsr, lr}
 
-// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, lr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
+// CHECK: clrm            {r0, r1, apsr}  @ encoding: [0x9f,0xe8,0x03,0x80]
+clrm {apsr, r1, r0}
+
+// CHECK: clrm            {r0, r1, r2, r3, r4, lr, apsr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
 clrm {r0-r4, apsr, lr}
 
 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.