[llvm] r368653 - [AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcOp. NFC.

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Mon Aug 12 23:55:32 2019
New Revision: 368653

URL: http://llvm.org/viewvc/llvm-project?rev=368653&view=rev
Log:
[AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcOp. NFC.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=368653&r1=368652&r2=368653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Aug 12 23:55:32 2019
@@ -2384,13 +2384,14 @@ bool AArch64InstructionSelector::selectT
   MIB.buildInstr(AArch64::LOADgot, {AArch64::X0}, {})
       .addGlobalAddress(&GV, 0, AArch64II::MO_TLS);
 
-  Register DestReg = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass);
-  MIB.buildInstr(AArch64::LDRXui, {DestReg}, {Register(AArch64::X0)}).addImm(0);
+  auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass},
+                             {Register(AArch64::X0)})
+                  .addImm(0);
 
   // TLS calls preserve all registers except those that absolutely must be
   // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
   // silly).
-  MIB.buildInstr(AArch64::BLR, {}, {DestReg})
+  MIB.buildInstr(AArch64::BLR, {}, {Load})
       .addDef(AArch64::X0, RegState::Implicit)
       .addRegMask(TRI.getTLSCallPreservedMask());