[PATCH] D66119: [GlobalISel]: Add KnownBits for G_XOR

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar created this revision.
aditya_nandakumar added reviewers: arsenm, dsanders, volkan, aemerson, paquette.
Herald added subscribers: Petar.Avramovic, hiraditya, rovka, wdng.
Herald added a project: LLVM.

Added test + implementation for knownBits for G_XOR.


Repository:
  rL LLVM

https://reviews.llvm.org/D66119

Files:
  llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
  llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp


Index: llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
===================================================================
--- llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -40,6 +40,22 @@
   EXPECT_EQ(256u, Res.One.getZExtValue());
   EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
 }
+TEST_F(GISelMITest, TestKnownBitsXOR) {
+  StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 4\n"
+                        "  %4:_(s8) = G_CONSTANT i8 7\n"
+                        "  %5:_(s8) = G_XOR %3, %4\n"
+                        "  %6:_(s8) = COPY %5\n";
+  setUp(MIRString);
+  if (!TM)
+    return;
+  unsigned CopyReg = Copies[Copies.size() - 1];
+  MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
+  unsigned SrcReg = FinalCopy->getOperand(1).getReg();
+  GISelKnownBits Info(*MF);
+  KnownBits Res = Info.getKnownBits(SrcReg);
+  EXPECT_EQ(3u, Res.One.getZExtValue());
+  EXPECT_EQ(252u, Res.Zero.getZExtValue());
+}
 
 TEST_F(GISelMITest, TestKnownBits) {
 
Index: llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -131,6 +131,19 @@
     Known.Zero.setLowBits(KnownZeroLow);
     break;
   }
+  case TargetOpcode::G_XOR: {
+    computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
+                         Depth + 1);
+    computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
+                         Depth + 1);
+
+    // Output known-0 bits are known if clear or set in both the LHS & RHS.
+    APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
+    // Output known-1 are known to be set if set in only one of the LHS, RHS.
+    Known.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
+    Known.Zero = KnownZeroOut;
+    break;
+  }
   // G_GEP is like G_ADD. FIXME: Is this true for all targets?
   case TargetOpcode::G_GEP:
   case TargetOpcode::G_ADD: {


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