[llvm] r368626 - [AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Mon Aug 12 15:32:21 2019
New Revision: 368626

URL: http://llvm.org/viewvc/llvm-project?rev=368626&view=rev
Log:
[AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.

This is infrastructural, will be needed for future work.
For some reason it was only used in MIMG_NoSampler, while
needed everywere we use MIMGBaseOpcode if we want to use
predicates.

Differential Revision: https://reviews.llvm.org/D66115

Modified:
    llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td

Modified: llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td?rev=368626&r1=368625&r2=368626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td Mon Aug 12 15:32:21 2019
@@ -26,7 +26,7 @@ def MIMGEncoding : GenericEnum {
 
 // Represent an ISA-level opcode, independent of the encoding and the
 // vdata/vaddr size.
-class MIMGBaseOpcode {
+class MIMGBaseOpcode : PredicateControl {
   MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
   bit Store = 0;
   bit Atomic = 0;
@@ -291,7 +291,7 @@ multiclass MIMG_NoSampler_Src_Helper <bi
 
 multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0,
                            bit isResInfo = 0> {
-  def "" : MIMGBaseOpcode, PredicateControl {
+  def "" : MIMGBaseOpcode {
     let Coordinates = !if(isResInfo, 0, 1);
     let LodOrClampOrMip = mip;
     let HasD16 = has_d16;