[PATCH] D66109: GlobalISel: Change representation of shuffle masks

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, aditya_nandakumar, paquette, dsanders, qcolombet.
Herald added subscribers: Petar.Avramovic, volkan, kristof.beyls, javed.absar, rovka, wdng.

Currently shufflemasks get emitted as any other constant, and you end
up with a bunch of virtual registers of G_CONSTANT with a
G_BUILD_VECTOR. The AArch64 selector then asserts on anything that
doesn't fit this pattern. This isn't an ideal representation, and
should avoid legalization and have fewer opportunities for a
representational error.

      

Rather than invent a new shuffle mask operand type, similar to what
ShuffleVectorSDNode does, just track the original IR Constant mask
operand. I don't completely like the idea of adding another link to
the IR, but MIR is already quite dependent on IR constants already,
and this will allow sharing the shuffle mask utility functions with
the IR.


https://reviews.llvm.org/D66109

Files:
  include/llvm/CodeGen/MachineInstrBuilder.h
  include/llvm/CodeGen/MachineOperand.h
  include/llvm/Target/GenericOpcodes.td
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineOperand.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/ARM/ARMExpandPseudoInsts.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
  test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
  test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
  test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
  test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
  test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir
  test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir
  test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir
  test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir
  test/CodeGen/MIR/AArch64/parse-shufflemask.mir
  test/MachineVerifier/test_g_shuffle_vector.mir

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