[llvm] r368558 - [X86][SSE] ComputeKnownBits - add basic PSADBW handling

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Aug 12 05:19:19 2019
New Revision: 368558

URL: http://llvm.org/viewvc/llvm-project?rev=368558&view=rev
Log:
[X86][SSE] ComputeKnownBits - add basic PSADBW handling

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/psadbw.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=368558&r1=368557&r2=368558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 12 05:19:19 2019
@@ -30974,12 +30974,21 @@ void X86TargetLowering::computeKnownBits
     Known.One |= Known2.One;
     break;
   }
+  case X86ISD::PSADBW: {
+    assert(VT.getScalarType() == MVT::i64 &&
+           Op.getOperand(0).getValueType().getScalarType() == MVT::i8 &&
+           "Unexpected PSADBW types");
+
+    // PSADBW - fills low 16 bits and zeros upper 48 bits of each i64 result.
+    Known.Zero.setBitsFrom(16);
+    break;
+  }
   case X86ISD::CMOV: {
-    Known = DAG.computeKnownBits(Op.getOperand(1), Depth+1);
+    Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
     // If we don't know any bits, early out.
     if (Known.isUnknown())
       break;
-    KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth+1);
+    KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
 
     // Only known if known in both the LHS and RHS.
     Known.One &= Known2.One;

Modified: llvm/trunk/test/CodeGen/X86/psadbw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/psadbw.ll?rev=368558&r1=368557&r2=368558&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/psadbw.ll (original)
+++ llvm/trunk/test/CodeGen/X86/psadbw.ll Mon Aug 12 05:19:19 2019
@@ -6,8 +6,7 @@
 define <2 x i64> @combine_psadbw_shift(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-LABEL: combine_psadbw_shift:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    psadbw %xmm1, %xmm0
-; CHECK-NEXT:    psrlq $48, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
   %4 = lshr <2 x i64> %3, <i64 48, i64 48>