[llvm] r368479 - [X86] Remove custom handling for extloads from LowerLoad.
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 9 14:07:00 PDT 2019
No worries, happens :)
-eric
On Fri, Aug 9, 2019 at 2:03 PM Topper, Craig <craig.topper at intel.com> wrote:
>
> Sorry about that. Thanks!
>
> -----Original Message-----
> From: Eric Christopher <echristo at gmail.com>
> Sent: Friday, August 9, 2019 2:03 PM
> To: Topper, Craig <craig.topper at intel.com>
> Cc: llvm-commits <llvm-commits at lists.llvm.org>
> Subject: Re: [llvm] r368479 - [X86] Remove custom handling for extloads from LowerLoad.
>
> Had a variable only used in an assert. Fixed in 368486.
>
> On Fri, Aug 9, 2019 at 1:26 PM Craig Topper via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> >
> > Author: ctopper
> > Date: Fri Aug 9 13:27:22 2019
> > New Revision: 368479
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=368479&view=rev
> > Log:
> > [X86] Remove custom handling for extloads from LowerLoad.
> >
> > We don't appear to need this with widening legalization.
> >
> > Modified:
> > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> >
> > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> > URL:
> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelL
> > owering.cpp?rev=368479&r1=368478&r2=368479&view=diff
> > ======================================================================
> > ========
> > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Aug 9 13:27:22
> > +++ 2019
> > @@ -877,19 +877,6 @@ X86TargetLowering::X86TargetLowering(con
> > setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
> > }
> >
> > - // We support custom legalizing of sext and anyext loads for specific
> > - // memory vector types which we can load as a scalar (or sequence of
> > - // scalars) and extend in-register to a legal 128-bit vector type. For sext
> > - // loads these must work with a single scalar load.
> > - for (MVT VT : MVT::integer_vector_valuetypes()) {
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
> > - setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
> > - }
> > -
> > for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
> > setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
> > setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
> > @@ -21458,176 +21445,7 @@ static SDValue LowerLoad(SDValue Op, con
> > return DAG.getMergeValues({Val, NewLd.getValue(1)}, dl);
> > }
> >
> > - // Nothing useful we can do without SSE2 shuffles.
> > - assert(Subtarget.hasSSE2() && "We only custom lower sext loads with
> > SSE2.");
> > -
> > - const TargetLowering &TLI = DAG.getTargetLoweringInfo();
> > - unsigned RegSz = RegVT.getSizeInBits();
> > -
> > - ISD::LoadExtType Ext = Ld->getExtensionType();
> > -
> > - assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
> > - && "Only anyext and sext are currently implemented.");
> > - assert(MemVT != RegVT && "Cannot extend to the same type");
> > - assert(MemVT.isVector() && "Must load a vector from memory");
> > -
> > - unsigned NumElems = RegVT.getVectorNumElements();
> > - unsigned MemSz = MemVT.getSizeInBits();
> > - assert(RegSz > MemSz && "Register size must be greater than the mem
> > size");
> > -
> > - if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget.hasInt256()) {
> > - // The only way in which we have a legal 256-bit vector result but not the
> > - // integer 256-bit operations needed to directly lower a sextload is if we
> > - // have AVX1 but not AVX2. In that case, we can always emit a sextload to
> > - // a 128-bit vector and a normal sign_extend to 256-bits that should get
> > - // correctly legalized. We do this late to allow the canonical form of
> > - // sextload to persist throughout the rest of the DAG combiner -- it wants
> > - // to fold together any extensions it can, and so will fuse a sign_extend
> > - // of an sextload into a sextload targeting a wider value.
> > - SDValue Load;
> > - if (MemSz == 128) {
> > - // Just switch this to a normal load.
> > - assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
> > - "it must be a legal 128-bit vector "
> > - "type!");
> > - Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
> > - Ld->getPointerInfo(), Ld->getAlignment(),
> > - Ld->getMemOperand()->getFlags());
> > - } else {
> > - assert(MemSz < 128 &&
> > - "Can't extend a type wider than 128 bits to a 256 bit vector!");
> > - // Do an sext load to a 128-bit vector type. We want to use the same
> > - // number of elements, but elements half as wide. This will end up being
> > - // recursively lowered by this routine, but will succeed as we definitely
> > - // have all the necessary features if we're using AVX1.
> > - EVT HalfEltVT =
> > - EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
> > - EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
> > - Load =
> > - DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
> > - Ld->getPointerInfo(), MemVT, Ld->getAlignment(),
> > - Ld->getMemOperand()->getFlags());
> > - }
> > -
> > - // Replace chain users with the new chain.
> > - assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
> > -
> > - // Finally, do a normal sign-extend to the desired register.
> > - SDValue SExt = DAG.getSExtOrTrunc(Load, dl, RegVT);
> > - return DAG.getMergeValues({SExt, Load.getValue(1)}, dl);
> > - }
> > -
> > - // All sizes must be a power of two.
> > - assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
> > - "Non-power-of-two elements are not custom lowered!");
> > -
> > - // Attempt to load the original value using scalar loads.
> > - // Find the largest scalar type that divides the total loaded size.
> > - MVT SclrLoadTy = MVT::i8;
> > - for (MVT Tp : MVT::integer_valuetypes()) {
> > - if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
> > - SclrLoadTy = Tp;
> > - }
> > - }
> > -
> > - // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
> > - if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
> > - (64 <= MemSz))
> > - SclrLoadTy = MVT::f64;
> > -
> > - // Calculate the number of scalar loads that we need to perform
> > - // in order to load our vector from memory.
> > - unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
> > -
> > - assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
> > - "Can only lower sext loads with a single scalar load!");
> > -
> > - unsigned loadRegSize = RegSz;
> > - if (Ext == ISD::SEXTLOAD && RegSz >= 256)
> > - loadRegSize = 128;
> > -
> > - // If we don't have BWI we won't be able to create the shuffle
> > needed for
> > - // v8i8->v8i64.
> > - if (Ext == ISD::EXTLOAD && !Subtarget.hasBWI() && RegVT == MVT::v8i64 &&
> > - MemVT == MVT::v8i8)
> > - loadRegSize = 128;
> > -
> > - // Represent our vector as a sequence of elements which are the
> > - // largest scalar that we can load.
> > - EVT LoadUnitVecVT = EVT::getVectorVT(
> > - *DAG.getContext(), SclrLoadTy, loadRegSize / SclrLoadTy.getSizeInBits());
> > -
> > - // Represent the data using the same element type that is stored in
> > - // memory. In practice, we ''widen'' MemVT.
> > - EVT WideVecVT =
> > - EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
> > - loadRegSize / MemVT.getScalarSizeInBits());
> > -
> > - assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
> > - "Invalid vector type");
> > -
> > - // We can't shuffle using an illegal type.
> > - assert(TLI.isTypeLegal(WideVecVT) &&
> > - "We only lower types that form legal widened vector types");
> > -
> > - SmallVector<SDValue, 8> Chains;
> > - SDValue Ptr = Ld->getBasePtr();
> > - unsigned OffsetInc = SclrLoadTy.getSizeInBits() / 8;
> > - SDValue Increment = DAG.getConstant(OffsetInc, dl,
> > - TLI.getPointerTy(DAG.getDataLayout()));
> > - SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
> > -
> > - unsigned Offset = 0;
> > - for (unsigned i = 0; i < NumLoads; ++i) {
> > - unsigned NewAlign = MinAlign(Ld->getAlignment(), Offset);
> > -
> > - // Perform a single load.
> > - SDValue ScalarLoad =
> > - DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr,
> > - Ld->getPointerInfo().getWithOffset(Offset),
> > - NewAlign, Ld->getMemOperand()->getFlags());
> > - Chains.push_back(ScalarLoad.getValue(1));
> > - // Create the first element type using SCALAR_TO_VECTOR in order to avoid
> > - // another round of DAGCombining.
> > - if (i == 0)
> > - Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
> > - else
> > - Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
> > - ScalarLoad, DAG.getIntPtrConstant(i, dl));
> > -
> > - Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
> > - Offset += OffsetInc;
> > - }
> > -
> > - SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
> > -
> > - // Bitcast the loaded value to a vector of the original element
> > type, in
> > - // the size of the target vector type.
> > - SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
> > - unsigned SizeRatio = RegSz / MemSz;
> > -
> > - if (Ext == ISD::SEXTLOAD) {
> > - SDValue Sext = getExtendInVec(ISD::SIGN_EXTEND, dl, RegVT, SlicedVec, DAG);
> > - return DAG.getMergeValues({Sext, TF}, dl);
> > - }
> > -
> > - if (Ext == ISD::EXTLOAD && !Subtarget.hasBWI() && RegVT == MVT::v8i64 &&
> > - MemVT == MVT::v8i8) {
> > - SDValue Sext = getExtendInVec(ISD::ZERO_EXTEND, dl, RegVT, SlicedVec, DAG);
> > - return DAG.getMergeValues({Sext, TF}, dl);
> > - }
> > -
> > - // Redistribute the loaded elements into the different locations.
> > - SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
> > - for (unsigned i = 0; i != NumElems; ++i)
> > - ShuffleVec[i * SizeRatio] = i;
> > -
> > - SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
> > - DAG.getUNDEF(WideVecVT), ShuffleVec);
> > -
> > - // Bitcast to the requested type.
> > - Shuff = DAG.getBitcast(RegVT, Shuff);
> > - return DAG.getMergeValues({Shuff, TF}, dl);
> > + return SDValue();
> > }
> >
> > /// Return true if node is an ISD::AND or ISD::OR of two
> > X86ISD::SETCC nodes
> >
> >
> > _______________________________________________
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