[PATCH] D65919: Add llvm-prefer-register-over-unsigned to clang-tidy and apply it to LLVM

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
dsanders added reviewers: arsenm, bogner.
Herald added subscribers: cfe-commits, s.egerton, Jim, asbirlea, Petar.Avramovic, jsji, jocewei, PkmX, tpr, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, asb, javed.absar, fedor.sergeev, kbarton, aheejin, hiraditya, kristof.beyls, jgravelle-google, sbc100, mgorny, nhaehnle, wdng, jvesely, nemanjai, sdardis, dylanmckay, jyknight, dschuff, qcolombet, MatzeB, jholewinski.
Herald added projects: clang, LLVM.

This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).

Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor

Manual fixups in:
AArch64InstrInfo.cpp - genFusedMultiply() now takes a Register* instead of unsigned*
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
AArch64LoadStoreOptimizer.cpp - Ternary operator was ambiguous between Register/MCRegister. Settled on Register
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D65919

Files:
  clang-tools-extra/clang-tidy/llvm/CMakeLists.txt
  clang-tools-extra/clang-tidy/llvm/LLVMTidyModule.cpp
  clang-tools-extra/clang-tidy/llvm/PreferRegisterOverUnsignedCheck.cpp
  clang-tools-extra/clang-tidy/llvm/PreferRegisterOverUnsignedCheck.h
  clang-tools-extra/docs/ReleaseNotes.rst
  clang-tools-extra/docs/clang-tidy/checks/list.rst
  clang-tools-extra/docs/clang-tidy/checks/llvm-prefer-register-over-unsigned.rst
  clang-tools-extra/test/clang-tidy/llvm-prefer-register-over-unsigned.cpp
  llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
  llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
  llvm/lib/CodeGen/BranchFolding.cpp
  llvm/lib/CodeGen/BreakFalseDeps.cpp
  llvm/lib/CodeGen/CalcSpillWeights.cpp
  llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
  llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
  llvm/lib/CodeGen/DetectDeadLanes.cpp
  llvm/lib/CodeGen/EarlyIfConversion.cpp
  llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
  llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
  llvm/lib/CodeGen/GlobalISel/Localizer.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/CodeGen/IfConversion.cpp
  llvm/lib/CodeGen/ImplicitNullChecks.cpp
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/LiveDebugValues.cpp
  llvm/lib/CodeGen/LiveDebugVariables.cpp
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/lib/CodeGen/LivePhysRegs.cpp
  llvm/lib/CodeGen/LiveRangeEdit.cpp
  llvm/lib/CodeGen/LiveRangeShrink.cpp
  llvm/lib/CodeGen/LiveRegMatrix.cpp
  llvm/lib/CodeGen/LiveRegUnits.cpp
  llvm/lib/CodeGen/LiveVariables.cpp
  llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/MachineCSE.cpp
  llvm/lib/CodeGen/MachineCopyPropagation.cpp
  llvm/lib/CodeGen/MachineInstrBundle.cpp
  llvm/lib/CodeGen/MachineLICM.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachinePipeliner.cpp
  llvm/lib/CodeGen/MachineSSAUpdater.cpp
  llvm/lib/CodeGen/MachineScheduler.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/MachineTraceMetrics.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/CodeGen/OptimizePHIs.cpp
  llvm/lib/CodeGen/PHIElimination.cpp
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/CodeGen/ProcessImplicitDefs.cpp
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/lib/CodeGen/RegisterPressure.cpp
  llvm/lib/CodeGen/RegisterScavenging.cpp
  llvm/lib/CodeGen/RenameIndependentSubregs.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/CodeGen/ShrinkWrap.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/StackMaps.cpp
  llvm/lib/CodeGen/TailDuplicator.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/CodeGen/TargetSchedule.cpp
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/lib/CodeGen/UnreachableBlockElim.cpp
  llvm/lib/CodeGen/VirtRegMap.cpp
  llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
  llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
  llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
  llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
  llvm/lib/Target/AArch64/AArch64FastISel.cpp
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
  llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
  llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
  llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
  llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
  llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
  llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
  llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
  llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
  llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
  llvm/lib/Target/AMDGPU/R600Packetizer.cpp
  llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
  llvm/lib/Target/ARC/ARCISelLowering.cpp
  llvm/lib/Target/ARC/ARCOptAddrMode.cpp
  llvm/lib/Target/ARC/ARCRegisterInfo.cpp
  llvm/lib/Target/ARM/A15SDOptimizer.cpp
  llvm/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMCallLowering.cpp
  llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.cpp
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp
  llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  llvm/lib/Target/ARM/MLxExpansionPass.cpp
  llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
  llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/lib/Target/AVR/AVRAsmPrinter.cpp
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRFrameLowering.cpp
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.cpp
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrInfo.cpp
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFRegisterInfo.cpp
  llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
  llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
  llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
  llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
  llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
  llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
  llvm/lib/Target/Hexagon/HexagonGenMux.cpp
  llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
  llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
  llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
  llvm/lib/Target/Hexagon/HexagonPeephole.cpp
  llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
  llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
  llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
  llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Hexagon/HexagonVExtract.cpp
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/lib/Target/Hexagon/RDFGraph.cpp
  llvm/lib/Target/Hexagon/RDFLiveness.cpp
  llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
  llvm/lib/Target/Lanai/LanaiFrameLowering.cpp
  llvm/lib/Target/Lanai/LanaiISelLowering.cpp
  llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
  llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
  llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
  llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
  llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
  llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
  llvm/lib/Target/Mips/Mips16ISelLowering.cpp
  llvm/lib/Target/Mips/MipsAsmPrinter.cpp
  llvm/lib/Target/Mips/MipsExpandPseudo.cpp
  llvm/lib/Target/Mips/MipsFastISel.cpp
  llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
  llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
  llvm/lib/Target/Mips/MipsSEISelLowering.cpp
  llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
  llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
  llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
  llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
  llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
  llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/Sparc/DelaySlotFiller.cpp
  llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/lib/Target/Sparc/SparcInstrInfo.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
  llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
  llvm/lib/Target/SystemZ/SystemZExpandPseudo.cpp
  llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
  llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
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