[PATCH] D65583: [ARM] MVE big endian loads/stores

Thu Aug 8 02:59:32 PDT 2019

samparker accepted this revision.
samparker added a comment.
This revision is now accepted and ready to land.

What an eye opener...

================
Comment at: llvm/test/CodeGen/Thumb2/mve-loadstore.ll:16
+; CHECK-BE-NEXT:    vshr.u32 q1, q0, #1
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
----------------
dmgreen wrote:
> samparker wrote:
> > So why not vrev32? I'm having real difficulty understanding why these vrev instructions are augmented with 'size'.
> These are just because we are returning a <4 x i32>, and the calling convention is a little odd at the moment. See the other BE patch in D65581.
> 
> The way I think of the vrevs is that the do 2 different bit level reverses. This one does on to i64's, then they are reversed again in i32's. So you end up with the bytes in the correct order, but re-arranged.
> 
> Point is that this one is not really the interesting part of this test. It is just an artifact of the calling convention.
cheers!

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65583/new/

https://reviews.llvm.org/D65583