[PATCH] D65583: [ARM] MVE big endian loads/stores

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:4789
+  def  : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
+             (v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
 }
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Do we support v2i1 as well?


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Comment at: llvm/test/CodeGen/Thumb2/mve-loadstore.ll:16
+; CHECK-BE-NEXT:    vshr.u32 q1, q0, #1
+; CHECK-BE-NEXT:    vrev64.32 q0, q1
+; CHECK-BE-NEXT:    bx lr
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So why not vrev32? I'm having real difficulty understanding why these vrev instructions are augmented with 'size'.


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  https://reviews.llvm.org/D65583/new/

https://reviews.llvm.org/D65583