[PATCH] D65884: [ARM] MVE Tail Predication

[Sam Parker via Phabricator via llvm-commits]

samparker marked an inline comment as done.
samparker added a comment.

> Why does the llvm_arm_vctp32 not return a <4xi1> directly?

The vctp family are defined like that because the ACLE specifies that they return a mve_pred16_t and I'm assuming this is a scalar - but I can't find a definition! I think that all the user facing predicate generators will produce a scalar and we will need to do the conversion to make it nice and LLVMy.

> Can you elaborate a little bit on this? I guess you mean instruction selection patterns to finally produce code? Can this work be committed without that being ready? I guess the question rephrased is: can you outline the plan?

The overall plan is as follows:

- Enable vectorizer.
- Teach the vectorizer to produce a predicated loop, using a pragma and a target profitability hook. Think we also need to specify that we support masked load/store intrinsics too.
- This pass converts some vector icmps to vctp intrinsics.
- A bit of isel for vctp and final bits for other MVE instructions.
- The loop is finalised in the LowOverheadLoop pass where we check for validity and remove the VCTP and VPST instructions, as well as their VPT blocks.
- Beer.





================
Comment at: include/llvm/IR/IntrinsicsARM.td:785
+
+def int_arm_mve_convert_pred : Intrinsic<[llvm_anyvector_ty], [llvm_i32_ty],
+                                         [IntrNoMem]>;
----------------
dmgreen wrote:
> This, at least in isel, is called a PREDICATE_CAST. (It used to be called a REINTERPRET_CAST, but I thought that name was overly broad). I think from IR a better name might be int_arm_mve_vmsr / int_arm_mve_vmrs, to represent that it is converting from a predicate to the scalar, as the instruction does.
Sounds good.


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https://reviews.llvm.org/D65884